R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 681

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

In configuration accesses, no interrupt is generated by a PCI master abort (no device connected).
A configuration write will end normally. A configuration read will return a value of 0.
(3)
In host mode, the PCI bus arbiter in the PCIC is activated.
The PCIC supports four external masters (four pairs of REQ and GNT).
If the bus usage is simultaneously requested by two devices or more, the bus arbiter accepts the
request of the highest priority device.
The PCI bus arbiter supports two modes to determine the device priority: (1) fixed priority and (2)
pseudo-round-robin. The mode is selected by the BMAM bit in PCICR.
In the following description, the device n indicates a PCI device that uses REQn.
(a) Fixed Priority: When the BMAM bit in PCICR is cleared to 0, the priorities of devices are
fixed by the default as follows:
PCIC > device 0 > device 1 > device 2 > device 3
The PCIC has the priority to use the bus in comparison with other devices.
(b) Pseudo-Round-Robin: When the BMAM bit in PCICR is set to 1, the most recently permitted
device is assigned as the lowest priority.
The initial priority is the same as that of the fixed priority mode.
After the device 1 requires the bus and transfer data and the request is permitted, the priority
changes as follows:
PCIC > device 0 > device 2 > device 3 > device 1
Arbitration
Configuration address
register
PCI bus address
Figure 13.17 Address Generation for Type 0 Configuration Access
Enable bit
0: Disabled
1: Enabled
31 30
31
Reserved
24
Only one bit is set to 1.
23
Bus No.
16
15
Device No.
Rev.1.00 Jan. 10, 2008 Page 649 of 1658
1110
1110
Function
No.
8 7
8 7
Register No. 0 0
13. PCI Controller (PCIC)
2 1 0
2 1 0
REJ09B0261-0100
0 0