R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 689

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. PCI Controller (PCIC)
(2)
Target Read/Write Cycle Timing
The PCIC returns retries to target memory read accesses from an external master until 8 longword
(32-bit) data are prepared in the PCIC internal FIFO. That is, the first target read is always
responded by a retry.
When a target memory write access is performed for the PCIC, the PCIC returns retries to all
subsequent target memory accesses until the write data is completely written to local memory.
Thus, the data contents are guaranteed when data written to the target is target-read immediately
after it was written.
Only single transfers are supported for target accesses to the configuration space and I/O space. If
a burst access request is issued, the external master is disconnected when the first transfer is
complete. Note that the DEVSEL response speed is fixed to 2 clocks (medium) for the target
access to the PCIC.
Figure 13.23 shows an example of a target single-read cycle in normal mode. Figure 13.24 shows
an example of a target single-write cycle in normal mode. Figure 13.25 shows an example of a
target burst-read cycle in host mode. Figure 13.26 shows an example of a target burst-write cycle
in host mode.
Rev.1.00 Jan. 10, 2008 Page 657 of 1658
REJ09B0261-0100