R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1172

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22. Serial I/O with FIFO (SIOF)
(2)
Figure 22.10 shows an example of settings and operation for master mode reception.
Rev.1.00 Jan. 10, 2008 Page 1140 of 1658
REJ09B0261-0100
Reception in Master Mode
No.
1
2
3
4
5
6
7
8
Store SIOF_RXD receive data in SIRDR
Set the FSE and RXE bits in SICTR to 1
synchronously with SIOF_SYNC
Clear the RXE bit in SICTR to 0
Set the SCKE bit in SICTR to 1
Figure 22.10 Example of Receive Operation in Master Mode
Set SIMDR, SISCR, SITDAR,
SIRDAR, SICDAR, SITCR,
Start SIOF_SCK output
Transfer ended?
Read SIRDR
and SIFCTR
RDREQ = 1
Flowchart
Start
End
Yes
Yes
No
No
Set operating mode, serial clock, slot
positions for transmit/receive data, slot
position for control data, and FIFO
request threshold value
Set operation start for baud rate generator
Set the start for frame synchronous signal
output and enable reception
Read receive data
Set to disable reception
SIOF Settings
Output serial clock
Output frame
synchronous signal
Issue receive transfer
request according to
the receive FIFO
threshold value
Receive
End reception
SIOF Operation