MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 159

• Manufacturer Part Number: MC68908GZ8MFAE
• Description: IC MCU 8BIT 8K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68908GZ8MFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Processor Series: M689xx
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 13-4
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a
logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
13.3.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each
of the eight port A pins. Each bit is individually configurable and requires that the data direction register,
DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRA is configured for output mode.
Freescale Semiconductor
1. X = Don’t care
2. I/O pin pulled up to V
3. Writing affects data register, but does not affect input.
4. Hi-Z = High impedance
PTAPUE
Bit
X
1
0
shows the port A I/O logic.
Address:
DDRA
Reset:
Read:
Write:
Bit
0
0
1
Figure 13-5. Port A Input Pullup Enable Register (PTAPUE)
DD
PTAPUEx
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
READ PTA ($0000)
PTAPUE7
$000D
by internal pullup device
Bit 7
0
PTA
X
Bit
X
X
(1)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
PTAPUE6
6
0
Input, Hi-Z
Input, V
Table 13-2. Port A Pin Functions
RESET
Figure 13-4. Port A I/O Circuit
I/O Pin
Output
Mode
V
DD
PTAPUE5
INTERNAL
PULLUP
DEVICE
DD
5
0
(2)
(4)
Table 13-2
PTAPUE4
DDRAx
Accesses to DDRA
PTAx
4
0
DDRA7–DDRA0
DDRA7–DDRA0
DDRA7–DDRA0
Read/Write
PTAPUE3
summarizes the operation of the port A pins.
3
0
PTAPUE2
2
0
PTA7–PTA0
Read
PTAPUE1
Pin
Pin
1
0
Accesses to PTA
PTAPUE0
Bit 0
PTAx
0
PTA7–PTA0
PTA7–PTA0
PTA7–PTA0
Write
Port A
(3)
(3)
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