MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 210
![IC MCU 8BIT 8K FLASH 48-LQFP](/photos/37/62/376278/tqfp-48_sml.jpg)
MC68908GZ8MFAE
Manufacturer Part Number
MC68908GZ8MFAE
Description
IC MCU 8BIT 8K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68908GZ8CFJER.pdf
(314 pages)
Specifications of MC68908GZ8MFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
M689xx
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Enhanced Serial Communications Interface (ESCI) Module
ARUN— Arbiter Counter Running Flag
AROVFL— Arbiter Counter Overflow Bit
ARD8— Arbiter Counter MSB
15.9.2 ESCI Arbiter Data Register
ARD7–ARD0 — Arbiter Least Significant Counter Bits
15.9.3 Bit Time Measurement
Two bit time measurement modes, described here, are available according to the state of ACLK.
210
1. ACLK = 0 — The counter is clocked with the bus clock divided by four. The counter is started when
2. ACLK = 1 — The counter is clocked with one quarter of the ESCI input clock generated by the ESCI
This read-only bit indicates the arbiter counter is running. Reset clears ARUN.
This read-only bit indicates an arbiter counter overflow. Clear AROVFL by writing any value to
SCIACTL. Writing logic 0s to AM1 and AM0 resets the counter keeps it in this idle state. Reset clears
AROVFL.
This read-only bit is the MSB of the 9-bit arbiter counter. Clear ARD8 by writing any value to SCIACTL.
Reset clears ARD8.
These read-only bits are the eight LSBs of the 9-bit arbiter counter. Clear ARD7–ARD0 by writing any
value to SCIACTL. Writing logic 0s to AM1 and AM0 permanently resets the counter and keeps it in
this idle state. Reset clears ARD7–ARD0.
1 = Arbiter counter running
0 = Arbiter counter stopped
1 = Arbiter counter overflow has occurred
0 = No arbiter counter overflow has occurred
a falling edge on the RxD pin is detected. The counter will be stopped on the next falling edge.
ARUN is set while the counter is running, AFIN is set on the second falling edge on RxD (for
instance, the counter is stopped). This mode is used to recover the received baud rate. See
Figure
prescaler. The counter is started when a logic 0 is detected on RxD (see
on RxD on enabling the bit time measurement with ACLK = 1 leads to immediate start of the
counter (see
is used to measure the length of a received break.
15-21.
Address: $000B
Reset:
Read:
Write:
Figure
ARD7
Bit 7
Figure 15-20. ESCI Arbiter Data Register (SCIADAT)
0
15-23). The counter will be stopped on the next rising edge of RxD. This mode
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
= Unimplemented
ARD6
6
0
ARD5
5
0
ARD4
4
0
ARD3
3
0
ARD2
2
0
ARD1
1
0
Figure
Freescale Semiconductor
ARD0
Bit 0
15-22). A logic 0
0
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