MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 56

IC MCU 8BIT 8K FLASH 48-LQFP

MC68908GZ8MFAE

Manufacturer Part Number
MC68908GZ8MFAE
Description
IC MCU 8BIT 8K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68908GZ8MFAE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
M689xx
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Analog-to-Digital Converter (ADC)
3.8.2.3 Left Justified Signed Data Mode
In left justified signed data mode, the ADRH register holds the eight MSBs of the 10-bit result. The only
difference from left justified mode is that the AD9 is complemented. The ADRL register holds the two
LSBs of the 10-bit result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single
channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. All
subsequent results will be lost until the ADRH and ADRL reads are completed.
3.8.2.4 Eight Bit Truncation Mode
In 8-bit truncation mode, the ADRL register holds the eight MSBs of the 10-bit result. The ADRH register
is unused and reads as 0. The ADRL register is updated each time an ADC single channel conversion
completes. In 8-bit mode, the ADRL register contains no interlocking with ADRH.
56
Address:
Address:
Address:
Address:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Figure 3-7. ADC Data Register High (ADRH) and Low (ADRL)
Figure 3-8. ADC Data Register High (ADRH) and Low (ADRL)
$003D
$003E
$003D
$003E
Bit 7
AD9
AD1
Bit 7
AD9
0
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
= Unimplemented
= Unimplemented
AD8
AD0
AD8
6
6
0
AD7
AD7
5
0
5
0
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
AD6
AD6
4
0
4
0
AD5
AD5
3
0
3
0
AD4
AD4
2
0
2
0
AD3
AD3
1
0
1
0
Freescale Semiconductor
ADRH
ADRL
Bit 0
AD2
Bit 0
AD2
0
0

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