MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 198
![IC MCU 8BIT 8K FLASH 48-LQFP](/photos/37/62/376278/tqfp-48_sml.jpg)
MC68908GZ8MFAE
Manufacturer Part Number
MC68908GZ8MFAE
Description
IC MCU 8BIT 8K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68908GZ8CFJER.pdf
(314 pages)
Specifications of MC68908GZ8MFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
M689xx
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 198 of 314
- Download datasheet (5Mb)
Enhanced Serial Communications Interface (ESCI) Module
PTY — Parity Bit
15.8.2 ESCI Control Register 2
ESCI control register 2 (SCC2):
SCTIE — ESCI Transmit Interrupt Enable Bit
TCIE — Transmission Complete Interrupt Enable Bit
SCRIE — ESCI Receive Interrupt Enable Bit
198
This read/write bit determines whether the ESCI generates and checks for odd parity or even parity
(see
•
•
•
•
•
This read/write bit enables the SCTE bit to generate ESCI transmitter CPU interrupt requests. Setting
the SCTIE bit in SCC2 enables the SCTE bit to generate CPU interrupt requests. Reset clears the
SCTIE bit.
This read/write bit enables the TC bit to generate ESCI transmitter CPU interrupt requests. Reset
clears the TCIE bit.
This read/write bit enables the SCRF bit to generate ESCI receiver CPU interrupt requests. Setting the
SCRIE bit in SCC2 enables the SCRF bit to generate CPU interrupt requests. Reset clears the
SCRIE bit.
1 = Odd parity
0 = Even parity
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
Enables these CPU interrupt requests:
–
–
–
–
Enables the transmitter
Enables the receiver
Enables ESCI wakeup
Transmits ESCI break characters
Table
SCTE bit to generate transmitter CPU interrupt requests
TC bit to generate transmitter CPU interrupt requests
SCRF bit to generate receiver CPU interrupt requests
IDLE bit to generate receiver CPU interrupt requests
Address: $0014
15-5). Reset clears the PTY bit.
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Reset:
Read:
Write:
SCTIE
Bit 7
0
Figure 15-11. ESCI Control Register 2 (SCC2)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
TCIE
6
0
SCRIE
5
0
NOTE
ILIE
4
0
TE
3
0
RE
2
0
RWU
1
0
Freescale Semiconductor
Bit 0
SBK
0
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