MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 227

• Manufacturer Part Number: MC68908GZ8MFAE
• Description: IC MCU 8BIT 8K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68908GZ8MFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Processor Series: M689xx
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period.
Figure 16-18
16.7 SIM Registers
The SIM has three memory-mapped registers.
Freescale Semiconductor
CGMXCLK
INT/BREAK
IAB
shows stop mode entry timing.
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
Note: Previous data can be operand data or the STOP opcode, depending
CPUSTOP
R/W
IDB
IAB
on the last instruction.
Figure 16-19. Stop Mode Recovery from Interrupt
Address
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
$FE00
$FE01
$FE03
STOP ADDR
STOP +1
Figure 16-18. Stop Mode Entry Timing
PREVIOUS DATA
Table 16-4. SIM Registers
STOP ADDR + 1
Figure 16-19
Register
SBFCR
SRSR
SBSR
STOP + 2
Table 16-4
STOP RECOVERY PERIOD
NOTE
NOTE
NEXT OPCODE
STOP + 2
shows stop mode recovery time from interrupt.
shows the mapping of these registers.
SAME
Access Mode
SP
User
User
User
SAME
SP – 1
SAME
SAME
SP – 2
SIM Registers
SP – 3
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