MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 166
![IC MCU 8BIT 8K FLASH 48-LQFP](/photos/37/62/376278/tqfp-48_sml.jpg)
MC68908GZ8MFAE
Manufacturer Part Number
MC68908GZ8MFAE
Description
IC MCU 8BIT 8K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68908GZ8CFJER.pdf
(314 pages)
Specifications of MC68908GZ8MFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
M689xx
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 166 of 314
- Download datasheet (5Mb)
Input/Output (I/O) Ports
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a
logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
13.6.3 Port D Input Pullup Enable Register
The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each
of the eight port D pins. Each bit is individually configurable and requires that the data direction register,
DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRD is configured for output mode.
166
1. X = Don’t care
2. I/O pin pulled up to V
3. Writing affects data register, but does not affect input.
4. Hi-Z = High impedance
PTDPUE
Bit
X
1
0
Address:
DDRD
Reset:
Read:
Write:
Bit
0
0
1
Figure 13-16. Port D Input Pullup Enable Register (PTDPUE)
DD
PTDPUE7
READ DDRD ($0007)
WRITE DDRD ($0007)
WRITE PTD ($0003)
READ PTD ($0003)
$000F
Bit 7
by internal pullup device.
0
PTDPUEx
PTD
X
Bit
X
X
(1)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
PTDPUE6
6
0
Input, Hi-Z
Input, V
Table 13-5. Port D Pin Functions
RESET
Figure 13-15. Port D I/O Circuit
I/O Pin
Output
Mode
PTDPUE5
DD
VDD
(2)
(4)
5
0
INTERNAL
PULLUP
DEVICE
Table 13-5
PTDPUE4
Accesses to DDRD
DDRDx
PTDx
DDRD7–DDRD0
DDRD7–DDRD0
DDRD7–DDRD0
4
0
Read/Write
PTDPUE3
summarizes the operation of the port D pins.
3
0
PTDPUE2
2
0
PTD7–PTD0
Read
Pin
Pin
PTDPUE1
Accesses to PTD
1
0
Freescale Semiconductor
PTDPUE0
PTDx
Bit 0
0
PTD7–PTD0
PTD7–PTD0
PTD7–PTD0
Write
(3)
(3)
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