MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 73
![IC MCU 8BIT 8K FLASH 48-LQFP](/photos/37/62/376278/tqfp-48_sml.jpg)
MC68908GZ8MFAE
Manufacturer Part Number
MC68908GZ8MFAE
Description
IC MCU 8BIT 8K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68908GZ8CFJER.pdf
(314 pages)
Specifications of MC68908GZ8MFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
M689xx
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (5Mb)
4.5.4 PLL Multiplier Select Register Low
The PLL multiplier select register low (PMSL) contains the programming information for the low byte of
the modulo feedback divider.
MUL7–MUL0 — Multiplier Select Bits
4.5.5 PLL VCO Range Select Register
The PLL VCO range select register (PMRS) contains the programming information required for the
hardware configuration of the VCO.
Freescale Semiconductor
These read/write bits control the low byte of the modulo feedback divider that selects the VCO
frequency multiplier, N. (See
be written when the PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers
configures the modulo feedback divider the same as a value of $0001. Reset initializes the register to
$40 for a default multiply value of 64.
Address:
Address:
For applications using 1–8 MHz reference frequencies this register must be
reprogrammed before enabling the PLL. The reset value of this register will
cause applications using 1–8 MHz reference frequencies to become
unstable if the PLL is enabled without programming an appropriate value.
The programmed value must not allow the VCO clock to exceed 32 MHz.
See
proper value for PMSL.
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
PMRS may be called PVRS on other HC08 derivatives.
Reset:
Reset:
Read:
Read:
Write:
Write:
4.3.6 Programming the PLL
$003A
$0038
Figure 4-7. PLL Multiplier Select Register Low (PMSL)
MUL7
VRS7
Bit 7
Bit 7
Figure 4-8. PLL VCO Range Select Register (PMRS)
0
0
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
4.3.3 PLL Circuits
MUL6
VRS6
6
1
6
1
MUL5
VRS5
5
0
5
0
for detailed instructions on choosing the
NOTE
NOTE
NOTE
and
MUL4
VRS4
4
0
4
0
4.3.6 Programming the
MUL3
VRS3
3
0
3
0
MUL2
VRS2
2
0
2
0
MUL1
VRS1
PLL.) MUL7–MUL0 cannot
1
0
1
0
MUL0
VRS0
Bit 0
Bit 0
0
0
CGM Registers
73
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