MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 238
![IC MCU 8BIT 8K FLASH 48-LQFP](/photos/37/62/376278/tqfp-48_sml.jpg)
MC68908GZ8MFAE
Manufacturer Part Number
MC68908GZ8MFAE
Description
IC MCU 8BIT 8K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68908GZ8CFJER.pdf
(314 pages)
Specifications of MC68908GZ8MFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
M689xx
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Serial Peripheral Interface (SPI) Module
The internal SPI clock in the master is a free-running derivative of the internal MCU clock. To conserve
power, it is enabled only when both the SPE and SPMSTR bits are set. SPSCK edges occur halfway
through the low time of the internal MCU clock. Since the SPI clock is free-running, it is uncertain where
the write to the SPDR occurs relative to the slower SPSCK. This uncertainty causes the variation in the
initiation delay shown in
maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for
DIV32, and 128 MCU bus cycles for DIV128.
238
SPSCK CYCLE
CPHA = 1
CPHA = 0
NUMBER
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
SPSCK
SPSCK
MOSI
BUS
BUS
BUS
BUS
BUS
Figure
Figure 17-8. Transmission Start Delay (Master)
TO SPDR
TO SPDR
TO SPDR
WRITE
WRITE
WRITE
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
TO SPDR
TO SPDR
WRITE
WRITE
17-8. This delay is no longer than a single SPI bit time. That is, the
EARLIEST
EARLIEST
EARLIEST
EARLIEST
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
LATEST
SPSCK = INTERNAL CLOCK ÷ 128;
SPSCK = INTERNAL CLOCK ÷ 32;
SPSCK = INTERNAL CLOCK ÷ 8;
INITIATION DELAY
128 POSSIBLE START POINTS
32 POSSIBLE START POINTS
8 POSSIBLE START POINTS
SPSCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
MSB
1
BIT 6
2
LATEST
LATEST
LATEST
BIT 5
3
Freescale Semiconductor
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