MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 281
![IC MCU 8BIT 8K FLASH 48-LQFP](/photos/37/62/376278/tqfp-48_sml.jpg)
MC68908GZ8MFAE
Manufacturer Part Number
MC68908GZ8MFAE
Description
IC MCU 8BIT 8K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68908GZ8CFJER.pdf
(314 pages)
Specifications of MC68908GZ8MFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
M689xx
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (5Mb)
20.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
20.3.1.5 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal,
it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal.
20.3.1.6 Baud Rate
The communication baud rate is controlled by the crystal frequency or external clock and the state of the
PTB4 pin (when IRQ is set to V
on IRQ and the reset vector blank, then the baud rate is independent of PTB4.
Table 20-1
effective baud rate is the bus frequency divided by 278. If using a crystal as the clock source, be aware
of the upper frequency limit that the internal clock module can handle. See
or
20.3.1.7 Commands
The monitor ROM firmware uses these commands:
Freescale Semiconductor
21.6 3.3-Vdc Electrical Characteristics
•
•
•
•
•
•
READ (read memory)
WRITE (write memory)
IREAD (indexed read)
IWRITE (indexed write)
READSP (read stack pointer)
RUN (run user program)
also lists external frequencies required to achieve a standard baud rate of 7200 bps. The
User
Monitor
Modes
START
BIT
Vector High
0
$FFFE
$FEFE
Reset
BIT 0
1
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
2
BIT 1
TST
MISSING STOP BIT
3
Vector Low
Figure 20-11. Monitor Data Format
) upon entry into monitor mode. If monitor mode was entered with V
$FFFF
$FEFF
Figure 20-12. Break Transaction
4
Reset
BIT 2
Table 20-2. Mode Differences
5
6
for this limit.
BIT 3
Vector High
7
$FFFC
$FEFC
Break
BIT 4
Functions
BIT 5
Vector Low
APPROXIMATELY 2 BITS DELAY
BEFORE ZERO ECHO
$FEFD
$FFFD
Break
BIT 6
0
1
BIT 7
2
Vector High
$FFFC
$FEFC
3
STOP
SWI
BIT
4
21.7 5.0-Volt Control Timing
START
NEXT
5
BIT
6
Vector Low
$FEFD
$FFFD
SWI
7
Monitor ROM (MON)
DD
281
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