MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 229

• Manufacturer Part Number: MC68908GZ8MFAE
• Description: IC MCU 8BIT 8K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68908GZ8MFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Processor Series: M689xx
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ILAD — Illegal Address Reset Bit (opcode fetches only)
MODRST — Monitor Mode Entry Module Reset Bit
LVI — Low-Voltage Inhibit Reset Bit
16.7.3 Break Flag Control Register
The break flag control register (BFCR) contains a bit that enables software to clear status bits while the
MCU is in a break state.
BCFE — Break Clear Flag Enable Bit
Freescale Semiconductor
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after
0 = POR or read of SRSR
1 = Last reset caused by the LVI circuit
0 = POR or read of SRSR
1 = Status bits clearable during break
0 = Status bits not clearable during break
POR while IRQ = V
Address:
Reset:
Read:
Write:
$FE03
BCFE
Bit 7
R
0
Figure 16-22. Break Flag Control Register (BFCR)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
DD
= Reserved
R
6
R
5
R
4
R
3
R
2
R
1
Bit 0
R
SIM Registers
229