LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 115

• Manufacturer Part Number: LFXP2-8E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 201
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 8000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 201
• Ram Bits: 226304
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Differential I/O Implementation
The LatticeXP2 devices support a variety of differential standards as detailed in the following sections.
LVDS
True LVDS (LVDS25) drivers are available on 50% of the I/Os on the left and right side of the devices. LVDS input
support is provided on all sides of the device. All four sides of the device support LVDS using complementary LVC-
MOS drivers with external resistors (LVDS25E). Refer to the
tion of these LVDS implementations.
BLVDS
All single-ended sysIO buffers pairs support the Bus-LVDS standard using complementary LVCMOS drivers with
external resistors. Please refer to the
tation.
RSDS
All single-ended sysIO buffers pairs support RSDS standard using complementary LVCMOS drivers with external
resistors. Please refer to the
LVPECL
All the sysIO buffers will support LVPECL inputs. LVPECL outputs are supported using complementary LVCMOS
driver with external resistors. Please refer to the
LVPECL implementation.
Differential SSTL and HSTL
All single-ended sysIO buffers pairs support differential SSTL and HSTL. Please refer to the
Data Sheet
MLVDS
All single-ended sysIO buffers pairs support MLVDS standard using complementary LVCMOS drivers with external
resistors. Please refer to the
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet:
Revision History
February 2007
February 2009
April 2008
[phone] (Outside North America)
[e-mail]
www.latticesemi.com
Date
for a detailed explanation of Differential HSTL and SSTL implementation.
LatticeXP2 Family Data Sheet
LatticeXP2 Family Data Sheet
Version
01.0
01.1
01.2
LatticeXP2 Family Data Sheet
Initial release.
Updated Supported Output Standards table.
Updated sysIO Banking figure.
Updated I/O Standards Supported by Bank table.
LatticeXP2 Family Data Sheet
8-11
for a detailed explanation of RSDS implementation.
for a detailed explanation of MLVDS implementation.
LatticeXP2 Family Data Sheet
for a detailed explanation of BLVDS implemen-
Change Summary
LatticeXP2 sysIO Usage Guide
for a detailed explanation of
for a detailed explana-
LatticeXP2 Family