LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 322

• Manufacturer Part Number: LFXP2-8E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 201
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 8000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 201
• Ram Bits: 226304
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeXP2 Dual Boot Feature
Dual Boot
The device has two patterns, namely a Primary pattern and a Golden pattern, to choose to load.
Refresh
The action loads the pattern from a non-volatile source to configure the FPGA device.
Bitstream Data File (.BIT File)
The configuration data file, for a single FPGA device, in the format that can be loaded directly into the FPGA device
to configure the SRAM cells. The file is expressed in binary hex format. The file is not printable.
JEDEC File (.JED File)
The programming data file as defined by JEDEC 42.1C standard. The programming file is expressed in the ASCII 1
and 0 format. The file is printable. Third party programmers use it to support large volume production programming.
TransFR
The feature allows users to precisely control the user IO pins (high, low, or tri-state) while the embedded Flash is
massively parallel loaded into the SRAM fuses.
Security
Standard security is the feature that disables the read back operation from the embedded Flash and SRAM blocks.
Advanced security refers to the features providing encryption support and various Keys and Locks for protecting
the Embedded Flash block.
SED CRC
Soft Error Detection (SED) by calculating the CRC value of the value of the SRAM fuses. Lattice implements the
feature by using a 32-bit polynomial.
One Shot SED
After each boot from the embedded Flash, this feature enables the SED CRC feature automatically and immedi-
ately checking the integrity of the embedded Flash content.
Background Mode (User Mode)
The FPGA device shall remain fully operational as governed by the fuse pattern residing in the SRAM fuse module
of the FPGA device at the time while programming activities being carried out on the FPGA device or the peripheral
device (SPI Flash device) attached to it. This mode is the most critical attributes of the live field upgrade feature
that can be found only on Lattice’s FPGA devices.
Direct Mode (IEEE 1532 Access Modal State)
The FPGA device shall be removed from the governing of the fuse pattern residing in the SRAM fuse module, or so
to say, put to sleep while programming activities being carried out on the FPGA device or on the peripheral device
(SPI Flash device) attached to it. The IOs are either tri-stated or held statically while in this mode. Lack of a better
term, Lattice uses it to contrast against the background mode. All PLD devices support this mode.
Purpose
It has been the ultimate goal for the In-System Programming revolution championed by Lattice since 1990 to pro-
vide a reliable and continuous live field upgradable system. The TransFR feature designed into Lattice devices
since 2000 brings Lattice closer to the ultimate goal. With the introduction of the dual boot feature and the
advanced security feature in 2007, the ultimate goal is achieved.
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