LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 294

• Manufacturer Part Number: LFXP2-8E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 201
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 8000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 201
• Ram Bits: 226304
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 14-3. Wake Up Sequence to Internal Clock
Synchronous to Internal Done Bit
If the LatticeXP2 device is the only device in the chain, or the last device in a chain, the wake up process should be
initiated by the completion of the configuration. Once the configuration is complete, the internal Done bit will be set
and then the wake up process will begin.
Synchronous to External DONE Signal
The DONE pin can be selected to delay wake up. If DONE_EX is true then the wake up sequence will be delayed
until the DONE pin is high. The device will then follow the WAKE_UP sequence selected. When the device is in the
SDM mode the DONE pin is not used and therefore the DONE_EX preference has no effect.
Software Selectable Options
In order to control the configuration of the LatticeXP2 device beyond the default settings, software preferences are
used. Table 14-7 is a list of the preferences with their default settings.
Table 14-7. Software Preference List for the LatticeXP2
Slave SPI Port
In order to use the Slave SPI port while in user mode to read SRAM or Flash memory, the SLAVE_SPI_PORT pref-
erence must be set to ENABLE. Setting this preference preserves the Slave SPI port pins so the FPGA can be
accessed by an external device while in user mode. This also lets the software know that the Slave SPI port pins
are reserved and NOT available for use by the fitter or the user.
GLOBAL OUTPUT ENABLE
GLOBAL WRITE DISABLE
SLAVE_SPI_PORT
MASTER_SPI_PORT
DONE_OD
DONE_EX
CONFIG_SECURE
WAKE_UP
WAKE_ON_LOCK
INBUF
GLOBAL SET/RESET
Preference Name
DONE PIN
DONE BIT
BCLK
DISABLE [disable, enable]
DISABLE [disable, enable]
ON [off, on]
OFF [off, on]
OFF [off, on]
21 (DONE_EX = off)
4 (DONE_EX = on)
OFF [off, on]
ON [off, on]
T0
14-12
Default Setting [List of All Settings]
T1
LatticeXP2 sysCONFIG Usage Guide
T2
T3