LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 189

• Manufacturer Part Number: LFXP2-8E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 201
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 8000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 201
• Ram Bits: 226304
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 10-44. PFU Based Distributed Dual Port RAM Timing Waveform - with Output Registers
Distributed ROM (Distributed_ROM) – PFU Based
PFU-based Distributed ROM is also created using the 4-input LUT (Look-Up Table) available in the PFU. These
LUTs can be cascaded to create larger Distributed Memory sizes.
Figure 10-45 shows the Distributed ROM module as generated by IPexpress.
Figure 10-45. Distributed ROM Generated by IPexpress
The generated module makes use of the 4-input LUT available in the PFU. Additional logic like Clock and Reset is
generated by utilizing the resources available in the PFU.
WrClockEn
RdClockEn
WrAddress
RdAddress
WrClock
RdClock
Reset
Data
WE
Q
t
t
t
t
SUWREN_PFU
SUWREN_PFU
SUADDR_PFU
SUDATA_PFU
Data_0
Add_0
OutClockEn
OutClock
t
t
t
Address
HWREN_PFU
HADDR_PFU
HDATA_PFU
Reset
Invalid Data
Data_1
Add_1
10-39
Distributed ROM
PFU-based
t
SUCE_PFU
Add_0
t
HWREN_PFU
LatticeXP2 Memory Usage Guide
t
CORAM_PFU
Q
Data_0
Add_1
Data_1
t
HCE_PFU