LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 2

• Manufacturer Part Number: LFXP2-8E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 201
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 8000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 201
• Ram Bits: 226304
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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April 2011
Section I. LatticeXP2 Family Data Sheet
Introduction
Architecture
Features ............................................................................................................................................................. 1-1
Introduction ........................................................................................................................................................ 1-2
Architecture Overview ........................................................................................................................................ 2-1
PFU Blocks ........................................................................................................................................................ 2-2
Routing............................................................................................................................................................... 2-6
sysCLOCK Phase Locked Loops (PLL) ............................................................................................................. 2-6
Clock Dividers .................................................................................................................................................... 2-7
Clock Distribution Network ................................................................................................................................. 2-8
sysMEM Memory ............................................................................................................................................. 2-16
sysDSP™ Block ............................................................................................................................................... 2-18
Optimized DSP Functions ................................................................................................................................ 2-25
Programmable I/O Cells (PIC) ......................................................................................................................... 2-26
PIO ................................................................................................................................................................... 2-27
Slice .......................................................................................................................................................... 2-3
Modes of Operation................................................................................................................................... 2-5
Primary Clock Sources.............................................................................................................................. 2-8
Secondary Clock/Control Sources .......................................................................................................... 2-10
Edge Clock Sources................................................................................................................................ 2-11
Primary Clock Routing ............................................................................................................................ 2-12
Dynamic Clock Select (DCS) .................................................................................................................. 2-12
Secondary Clock/Control Routing ........................................................................................................... 2-12
Slice Clock Selection............................................................................................................................... 2-14
Edge Clock Routing ................................................................................................................................ 2-15
sysMEM Memory Block........................................................................................................................... 2-16
Bus Size Matching .................................................................................................................................. 2-16
FlashBAK EBR Content Storage............................................................................................................. 2-16
Memory Cascading ................................................................................................................................. 2-17
Single, Dual and Pseudo-Dual Port Modes............................................................................................. 2-17
Memory Core Reset ................................................................................................................................ 2-17
EBR Asynchronous Reset....................................................................................................................... 2-18
sysDSP Block Approach Compare to General DSP ............................................................................... 2-18
sysDSP Block Capabilities ...................................................................................................................... 2-19
MULT sysDSP Element .......................................................................................................................... 2-20
MAC sysDSP Element ............................................................................................................................ 2-21
MULTADDSUB sysDSP Element ........................................................................................................... 2-22
MULTADDSUBSUM sysDSP Element ................................................................................................... 2-23
Clock, Clock Enable and Reset Resources ............................................................................................ 2-23
Signed and Unsigned with Different Widths............................................................................................ 2-24
OVERFLOW Flag from MAC .................................................................................................................. 2-24
IPexpress™............................................................................................................................................. 2-25
Resources Available in the LatticeXP2 Family........................................................................................ 2-25
LatticeXP2 DSP Performance................................................................................................................. 2-25
Input Register Block ................................................................................................................................ 2-27
Output Register Block ............................................................................................................................. 2-28
Tristate Register Block ............................................................................................................................ 2-30
LatticeXP2 Family Handbook
1
Table of Contents