LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 171

• Manufacturer Part Number: LFXP2-8E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 201
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 8000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 201
• Ram Bits: 226304
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
The various ports and their definitions for the ROM are listed in Table 10-11. The table lists the corresponding ports
for the module generated by IPexpress and for the ROM primitive.
Table 10-11. EBR-based ROM Port Definitions
Reset (RST) resets only the input and output registers of the RAM. It does not reset the contents of the memory.
Chip Select (CS) is a useful port when multiple cascaded EBR blocks are required by the memory. The CS signal
forms the MSB for the address when multiple EBR blocks are cascaded. Since CS is a 3-bit bus, it can cascade
eight memories easily. However, if the memory size specified by the user requires more than eight EBR blocks, the
ispLEVER software automatically generates the additional address decoding logic, which is implemented in the
PFU external to the EBR blocks.
While generating the ROM using IPexpress, the user must provide the initialization file to pre-initialize the contents
of the ROM. These files are the *.mem files and they can be of Binary, Hex or the Addressed Hex formats. The ini-
tialization files are discussed in detail in the Initializing Memory section of this document.
Users have the option of enabling the output registers for Read Only Memory (ROM). Figures 10-19 and 10-20
show the internal timing waveforms for the Read Only Memory (ROM) with these options.
Each EBR block consists of 18,432 bits of RAM. The values for x’s (for address) and y’s (data) for each EBR block
for the devices are as per Table 10-12.
Table 10-12. ROM Memory Sizes for 16K Memory for LatticeXP2
Table 10-13 shows the various attributes available for the Read Only Memory (ROM). Some of these attributes are
user-selectable through the IPexpress GUI. For detailed attribute definitions, refer to Appendix A.
in Generated Module
OutClockEn
Port Name
OutClock
Address
Reset
—
512 x 36
16K x 1
1K x 18
8K x 2
4K x 4
2K x 9
ROM
EBR block Primitive
Port Name in the
AD[x:0]
CS[2:0]
CLK
RST
CE
Output Data
DOA[17:0]
DOA[35:0]
DOA[1:0]
DOA[3:0]
DOA[8:0]
10-21
DOA
Read Address
Clock Enable
Description
Chip Select
Reset
Clock
LatticeXP2 Memory Usage Guide
Address Port
[MSB:LSB]
WAD[13:0]
WAD[12:0]
WAD[11:0]
WAD[10:0]
WAD[9:0]
WAD[8:0]
Rising Clock Edge
Active State
Active High
Active High
—
—