LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 195

• Manufacturer Part Number: LFXP2-8E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 201
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 8000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 201
• Ram Bits: 226304
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 10-50. READ_ID Waveform
WRITE_EN (ACh)
The WRITE_EN command enables the TAG memory for programming. If the WRITE_EN command has not been
shifted into the device first, the PROGRAM_TAG, ERASE_TAG and STATUS commands do not take effect. This is
to prevent the TAG memory from erroneous erase or program.
The command is executed when the Chip Select pin is driven from low to high after the 24th dummy clock. Any
extra dummy clocks, if presented before driving the Chip Select pin to high, are ignored. After the Chip Select pin is
driven from low to high, a minimum of three clocks are required to complete the execution of the command.
The effect of this command is terminated by the WRITE_DIS command.
Figure 10-51. WRITE_EN Waveform
WRITE_DIS (78h)
The WRITE_DIS command disables the TAG memory for programming. It does not nullify the READ_TAG and
READ_ID commands.
The command is executed when the Chip Select pin is driven from low to high after the 24th dummy clock. Any
extra dummy clocks, if presented before driving the Chip Select pin to high, are ignored. After the Chip Select pin is
driven from low to high, a minimum of three clocks are required to complete the execution of the command.
CS
CLK
SI
SO
CS
CLK
SI
SO
8 Bits READ_ID
Command
Shifting Clocks
8 Command
3 Clocks To Initiate And Complete
24 Bits Dummy
HI-Z
Optional Extra Clocks
10-45
HIGH IMPEDANCE
0 1 2
32 Bits JTAG IDCODE
LatticeXP2 Memory Usage Guide
31
HI-Z