LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 295

FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd

LFXP2-8E-5FTN256I

Manufacturer Part Number
LFXP2-8E-5FTN256I
Description
FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet

Specifications of LFXP2-8E-5FTN256I

Number Of Macrocells
8000
Number Of Programmable I/os
201
Data Ram Size
226304
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FTBGA-256
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
226304
Number Of I /o
201
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Package
256FTBGA
Family Name
LatticeXP2
Device Logic Units
8000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
201
Ram Bits
226304
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFXP2-8E-5FTN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Master SPI Port
In order to use the Master SPI Port for configuration, the MASTER_SPI_PORT preference should be set to
ENABLE.
Configuration Mode
The device knows which physical sysCONFIG port will be used by reading the state of the CFG[1:0] pins, but the
fitter software also needs to know which port will be used. The fitter will determine the configuration mode based
upon the setting of the SLAVE_SPI_PORT and the MASTER_SPI_PORT preferences. The user may set these
preferences, and the ones listed below, using the Design Planner tool.
There are several additional configuration options, such as overflow, that are set by software. These options are
selected by clicking Properties under Generate Bitstream Data in ispLEVER. If either overflow option is selected,
then the DONE_EX and WAKE_UP selections will be set to correspond (see Table 14-8). Refer to the Configura-
tion Modes and Options section of this document for more details.
Table 14-8. Overflow Option Defaults
DONE Open Drain
The “DONE_OD” preference allows the user to configure the DONE pin as an open drain pin. The “DONE_OD”
preference is only used for the DONE pin. When the DONE pin is driven low, internally or externally, this indicates
that configuration is not complete and the device is not ready for the wake up sequence. Once configuration is com-
plete, with no errors, and the device is ready for wake up, the DONE pin must be driven high. For other devices to
be able to control the wake up process an open drain configuration is needed to avoid contention on the DONE pin.
The “DONE_OD” preference for the DONE pin defaults to ON. The DONE_OD preference is automatically set to
ON if the DONE_EX preference is set to ON. See Table 14-9 for more information on the relationship between
DONE_OD and DONE_EX. When the device is in the SDM mode the DONE pin is not used and therefore the
DONE_OD and DONE_EX preferences have no effect.
DONE External
The LatticeXP2 device can wake up on its own after the Done bit is set or wait for the DONE pin to be driven high
externally. Set DONE_EX = ON to delay wake up until the DONE pin is driven high by an external signal synchro-
nous to the clock; select OFF to synchronously wake up when the internal Done bit is set and ignore any external
driving of the DONE pin. The default is DONE_EX = OFF. If DONE_EX is set to ON, DONE_OD will be set to ON.
If an external signal is driving the DONE pin it should be open drain as well (an external pull-up resistor may need
to be added). See Table 14-9 for more information on the relationship between DONE_OD and DONE_EX.
Table 14-9. Summary of DONE Pin Preferences
Master Clock Selection
When the user has determined that the LatticeXP2 will be a master configuration device (by properly setting the
CFG[1:0] pins), and therefore provide the source clocking for configuration, the CCLK pin becomes an output with
the frequency set by the value in MCCLK_FREQ. At the start of configuration the device operates at the default
Overflow Option
On (either)
Off
Off
1. When the device is in the SDM mode the DONE pin is not used and therefore the DONE_OD and
DONE_EX preferences have no effect.
Off (Default)
On
On (automatically set by software)
DONE_EX
OFF
ON
1
DONE_EX Preference
External DONE low delays
External DONE ignored
Wake Up Process
14-13
Default 21 (user selectable 1 through 25)
Default 21 (user selectable 1 through 25)
Default 4 (User selectable 1 through 7)
LatticeXP2 sysCONFIG Usage Guide
Set to Default (ON)
WAKE_UP Preference
User selected
DONE_OD
1

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