LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 150

• Manufacturer Part Number: LFXP2-8E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 201
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 8000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 201
• Ram Bits: 226304
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
For example:
If phase adjustment of -90° of CLKOS is desired, a user can set the Phase to 270° and set the INPUT_SETUP
preference with PLL_PHASE_BACK.
PLL_PHASE_BACK Usage in Pre-Map Preference Editor
The Pre-Map Preference Editor can be used to set the PLL_PHASE_BACK attribute.
The INPUT_SETUP/CLOCK_TO_OUT Preference window is shown in Figure 9-25.
Figure 9-25. INPUT_SETUP/CLOCK_TO_OUT Preference Window
1. Open the Design Planner (Pre-Map).
2. In the Design Planner control window, select View -> Spreadsheet View.
3. In the Spreadsheet View window, select Input_setup/Clock_to_out...
9-28
LatticeXP2 sysCLOCK PLL
Design and Usage Guide