YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 103

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, refer to section 3, MCU Operating Modes.
2.1
• Upward-compatibility with H8/300 and H8/300H CPUs
• General-register architecture
• Sixty-five basic instructions
• Eight addressing modes
• 16-Mbyte address space
• High-speed operation
CPUS211A_000020020400
⎯ Can execute H8/300 and H8/300H CPU object programs
⎯ Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
⎯ 8/16/32-bit arithmetic and logic instructions
⎯ Multiply and divide instructions
⎯ Powerful bit-manipulation instructions
⎯ Register direct [Rn]
⎯ Register indirect [@ERn]
⎯ Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
⎯ Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
⎯ Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
⎯ Immediate [#xx:8, #xx:16, or #xx:32]
⎯ Program-counter relative [@(d:8,PC) or @(d:16,PC)]
⎯ Memory indirect [@@aa:8]
⎯ Program: 16 Mbytes
⎯ Data: 16 Mbytes
⎯ All frequently-used instructions are executed in one or two states
⎯ 8/16/32-bit register-register add/subtract: 1 state
⎯ 8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)
⎯ 16 ÷ 8-bit register-register divide: 12 states (DIVXU.B)
Features
Section 2 CPU
Rev.7.00 Mar. 18, 2009 page 35 of 1136
REJ09B0109-0700
Section 2 CPU