YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 288

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 6 Bus Controller (BSC)
6.7.5
When the DCTL pin is fixed to 1, synchronous clock (SDRAMφ) is output from the CS5 pin.
When the frequency multiplication factor of the PLL circuit of this LSI is set to ×1 or ×2,
SDRAMφ is 90° phase shift from φ. Therefore, a stable margin is ensured for the synchronous
DRAM that operates at the rising edge of clocks. Figure 6.43 shows the relationship between φ
and SDRAMφ. When the frequency multiplication factor of the PLL circuit is ×4, the phase of
SDRAMφ and that of φ are the same.
When the CLK pin of the synchronous DRAM is directly connected to SDRAMφ of this LSI, it is
recommended to set the frequency multiplication factor of the PLL circuit to ×1 or ×2.
Note: SDRAMφ output timing is shown when the frequency multiplication factor of the PLL
6.7.6
The four states of the basic timing consist of one T
output cycle) state, and the T
When areas 2 to 5 are set for the continuous synchronous DRAM space, settings of the WAITE bit
of BCR, RAST, CAST, RCDM bits of DRAMCR, and the CBRM bit of REFCR are ignored.
Figure 6.44 shows the basic timing for synchronous DRAM.
Rev.7.00 Mar. 18, 2009 page 220 of 1136
REJ09B0109-0700
Figure 6.43 Relationship between φ and SDRAMφ (when PLL Frequency Multiplication
circuit is ×1 or ×2.
Synchronous DRAM Clock
Basic Timing
SDRAMφ
φ
c1
and two T
Factor Is ×1 or ×2)
c2
(column address output cycle) states.
T cyc
p
(precharge cycle) state, one T
1/4 T cyc (90°)
r
(row address