YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 38

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.5 Multiprocessor Communication Function.......................................................................... 734
15.6 Operation in Clocked Synchronous Mode ......................................................................... 740
15.7 Operation in Smart Card Interface Mode........................................................................... 748
15.8 IrDA Operation .................................................................................................................. 759
15.9 Interrupt Sources ................................................................................................................ 762
15.10 Usage Notes ....................................................................................................................... 765
Section 16 I
16.1 Features .............................................................................................................................. 771
16.2 Input/Output Pins ............................................................................................................... 773
16.3 Register Descriptions ......................................................................................................... 774
Rev.7.00 Mar. 18, 2009 page xxxvi of lxvi
REJ09B0109-0700
15.4.6 Serial Data Reception (Asynchronous Mode)....................................................... 730
15.5.1 Multiprocessor Serial Data Transmission ............................................................. 735
15.5.2 Multiprocessor Serial Data Reception .................................................................. 737
15.6.1 Clock..................................................................................................................... 740
15.6.2 SCI Initialization (Clocked Synchronous Mode) .................................................. 741
15.6.3 Serial Data Transmission (Clocked Synchronous Mode) ..................................... 741
15.6.4 Serial Data Reception (Clocked Synchronous Mode)........................................... 744
15.6.5 Simultaneous Serial Data Transmission and Reception
15.7.1 Pin Connection Example....................................................................................... 748
15.7.2 Data Format (Except for Block Transfer Mode) ................................................... 749
15.7.3 Block Transfer Mode ............................................................................................ 750
15.7.4 Receive Data Sampling Timing and Reception Margin........................................ 750
15.7.5 Initialization .......................................................................................................... 752
15.7.6 Data Transmission (Except for Block Transfer Mode) ......................................... 753
15.7.7 Serial Data Reception (Except for Block Transfer Mode) .................................... 755
15.7.8 Clock Output Control............................................................................................ 757
15.9.1 Interrupts in Normal Serial Communication Interface Mode................................ 762
15.9.2 Interrupts in Smart Card Interface Mode .............................................................. 764
15.10.1 Module Stop Mode Setting ................................................................................... 765
15.10.2 Break Detection and Processing ........................................................................... 765
15.10.3 Mark State and Break Sending.............................................................................. 765
15.10.4 Receive Error Flags and Transmit Operations
15.10.5 Relation between Writes to TDR and the TDRE Flag .......................................... 766
15.10.6 Restrictions on Use of DMAC or DTC................................................................. 766
15.10.7 Operation in Case of Mode Transition.................................................................. 767
16.3.1 I
16.3.2 I
16.3.3 I
(Clocked Synchronous Mode) .............................................................................. 746
(Clocked Synchronous Mode Only)...................................................................... 766
2
2
2
2
C Bus Control Register A (ICCRA) ................................................................... 775
C Bus Control Register B (ICCRB) ................................................................... 777
C Bus Mode Register (ICMR)............................................................................ 778
C Bus Interface 2 (IIC2) (Option)................................................. 771