YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 659

KIT DEV EVAL H8S/2378 LCD

YLCDRSK2378

Manufacturer Part Number
YLCDRSK2378
Description
KIT DEV EVAL H8S/2378 LCD
Manufacturer
Renesas Electronics America
Series
H8®r
Datasheet

Specifications of YLCDRSK2378

Main Purpose
Displays, LCD Controller
Embedded
Yes, MCU, 16-Bit
Utilized Ic / Part
YLCDRSK2378
Primary Attributes
5.7" QVGA, Touch Screen
Secondary Attributes
Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Example of Synchronous Operation: Figure 11.11 shows an example of synchronous operation.
In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to
2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and
synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this
time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, is performed
for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle.
For details on PWM modes, see section 11.4.5, PWM Modes.
11.4.3
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or a compare match register.
Table 11.28 shows the register combinations used in buffer operation.
TGRB_0
TGRB_1
TGRA_0
TGRB_2
TGRA_1
TGRA_2
H'0000
TIOCA_0
TIOCA_1
TIOCA_2
Buffer Operation
TCNT0 to TCNT2 values
Figure 11.11 Example of Synchronous Operation
Synchronous clearing by TGRB_0 compare match
Rev.7.00 Mar. 18, 2009 page 591 of 1136
Section 11 16-Bit Timer Pulse Unit (TPU)
REJ09B0109-0700
Time

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