YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 295
YLCDRSK2378
Manufacturer Part Number
YLCDRSK2378
Description
KIT DEV EVAL H8S/2378 LCD
Manufacturer
Renesas Electronics America
Series
H8®r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of YLCDRSK2378
Main Purpose
Displays, LCD Controller
Embedded
Yes, MCU, 16-Bit
Utilized Ic / Part
YLCDRSK2378
Primary Attributes
5.7" QVGA, Touch Screen
Secondary Attributes
Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 295 of 1208
- Download datasheet (8Mb)
Section 6 Bus Controller (BSC)
6.7.10
Bus Cycle Control in Write Cycle
By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is
inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled.
Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to
synchronous DRAM read access. Figure 6.48 shows the write access timing when the CAS
latency control cycle is disabled.
T
T
T
T
p
r
c1
c2
φ
SDRAMφ
Address bus
Column address
Row address
Column address
Precharge-sel
Row address
RAS
CAS
WE
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
Figure 6.48 Example of Write Access Timing when CAS Latency Control Cycle Is Disabled
(SDWCD = 1)
Rev.7.00 Mar. 18, 2009 page 227 of 1136
REJ09B0109-0700
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