YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 826

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 15 Serial Communication Interface (SCI, IrDA)
When turning on the power or switching between Smart Card interface mode and software standby
mode, the following procedures should be followed in order to maintain the clock duty cycle.
Powering On: To secure the clock duty cycle from power-on, the following switching procedure
should be followed.
1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor
2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card mode operation.
4. Set the CKE0 bit in SCR to 1 to start clock output.
When Changing from Smart Card Interface Mode to Software Standby Mode:
1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to
2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive
3. Write 0 to the CKE0 bit in SCR to halt the clock.
4. Wait for one serial clock period.
5. Make the transition to the software standby state.
When Returning to Smart Card Interface Mode from Software Standby Mode:
1. Exit the software standby state.
2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the
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REJ09B0109-0700
to fix the potential.
the value for the fixed output state in software standby mode.
operation. At the same time, set the CKE1 bit to the value for the fixed output state in software
standby mode.
During this interval, clock output is fixed at the specified level, with the duty cycle preserved.
normal duty cycle.
[1] [2] [3]
Normal operation
Figure 15.32 Clock Halt and Restart Procedure
[4] [5]
Software
standby
[6]
[7]
Normal operation