YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 284

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 6 Bus Controller (BSC)
6.7
In the H8S/2378R Group, external address space areas 2 to 5 can be designated as continuous
synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous
DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous
DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR.
Synchronous DRAM of CAS latency 1 to 4 can be connected.
Note: The synchronous DRAM interface is not supported by the H8S/2378 Group.
6.7.1
Areas 2 to 5 are designated as continuous synchronous DRAM space by setting bits RMTS2 to
RMTS0 in DRAMCR. The relation between the settings of bits RMTS2 to RMTS0 and
synchronous DRAM space is shown in table 6.7. Possible synchronous DRAM interface settings
are and continuous area (areas 2 to 5).
Table 6.7
With continuous synchronous DRAM space, CS2, CS3, CS4 pins are used as RAS, CAS, WE
signal. The (OE) pin of the synchronous DRAM is used as the CKE signal, and the CS5 pin is
used as synchronous DRAM clock (SDRAMφ). The bus specifications for continuous
synchronous DRAM space conform to the settings for area 2. The pin wait and program wait for
the continuous synchronous DRAM are invalid.
Commands for the synchronous DRAM can be specified by combining RAS, CAS, WE, and
address-precharge-setting command (Precharge-sel) output on the upper column addresses.
Rev.7.00 Mar. 18, 2009 page 216 of 1136
REJ09B0109-0700
RMTS2
0
1
Synchronous DRAM Interface
Setting Continuous Synchronous DRAM Space
RMTS1
Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous DRAM
Space
0
1
0
1
RMTS0
1
0
1
0
1
0
1
Normal space Normal space Normal space
Normal space Normal space
DRAM space
Area 5
Continuous synchronous DRAM space
Mode settings of synchronous DRAM
DRAM space
Reserved (setting prohibited)
Continuous DRAM space
Area 4
DRAM space
DRAM space
Area 3
DRAM space
DRAM space
DRAM space
Area 2