YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 302

KIT DEV EVAL H8S/2378 LCD

YLCDRSK2378

Manufacturer Part Number
YLCDRSK2378
Description
KIT DEV EVAL H8S/2378 LCD
Manufacturer
Renesas Electronics America
Series
H8®r
Datasheet

Specifications of YLCDRSK2378

Main Purpose
Displays, LCD Controller
Embedded
Yes, MCU, 16-Bit
Utilized Ic / Part
YLCDRSK2378
Primary Attributes
5.7" QVGA, Touch Screen
Secondary Attributes
Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 6 Bus Controller (BSC)
6.7.13
This LSI is provided with a synchronous DRAM refresh control function. Auto refreshing is used.
In addition, self-refreshing can be executed when the chip enters the software standby state.
Refresh control is enabled when any area is designated as continuous synchronous DRAM space
in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR.
Auto Refreshing: To select auto refreshing, set the RFSHE bit to 1 in REFCR.
With auto refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0
in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control
is performed. At the same time, RTCNT is reset and starts counting up again from H'00.
Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0.
Rev.7.00 Mar. 18, 2009 page 234 of 1136
REJ09B0109-0700
Precharge-sel
DQMU, DQML
Address bus
Refresh Control
Data bus
CKE
CAS
RAS
WE
Figure 6.53 Example of Operation Timing in RAS Down Mode
φ
PALL ACTV READ
Continuous synchronous
DRAM space read
address
Column
T
p
address
address
Row
Row
T
r
(BE = 1, CAS Latency 2)
T
c1
Column address
T
cl
T
c2
High
NOP
External
space read
External address
External address
T
1
T
2
READ
Continuous synchronous
DRAM space read
T
c1
Column address 2
T
cl
NOP
T
c2

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