XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 156

IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112

XC68HC12A0CPV8

Manufacturer Part Number
XC68HC12A0CPV8
Description
IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of XC68HC12A0CPV8

Controller Family/series
68HC12
No. Of I/o's
68
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
1
Core Size
16 Bit
Program Memory Size
60KB
Peripherals
ADC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Clock Functions
11.6.15 PLL Register Descriptions
SYNR — Synthesizer Register
REFDV — Reference Divider Register
CGTFLG — Clock Generator Test Register
Technical Data
156
RESET:
RESET:
RESET:
TSTOUT7
Bit 7
Bit 7
Bit 7
0
0
0
0
0
TSTOUT6
6
0
0
6
0
0
6
0
Read anytime, write anytime, except when BCSP = 1 (PLL selected as
bus clock).
If the PLL is on, the count in the loop divider (SYNR) register effectively
multiplies up the bus frequency from the PLL reference frequency by
SYNR + 1. Internally, SYSCLK runs at twice the bus frequency. Caution
should be used not to exceed the maximum rated operating frequency
for the CPU.
Read anytime, write anytime, except when BCSP = 1.
The reference divider bits provides a finer granularity for the PLL
multiplier steps. The reference frequency is divided by REFDV + 1.
Always reads zero, except in test modes.
TSTOUT5
SYN5
5
0
5
0
0
5
0
TSTOUT4
SYN4
Clock Functions
4
0
4
0
0
4
0
TSTOUT3
SYN3
3
0
3
0
0
3
0
TSTOUT2
REFDV2
SYN2
2
0
2
0
2
0
TSTOUT1
REFDV1
SYN1
MC68HC912D60A — Rev. 3.1
1
0
1
0
1
0
Freescale Semiconductor
TSTOUT0
REFDV0
SYN0
Bit 0
Bit 0
Bit 0
0
0
0
$003A
$0038
$0039

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