XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 258

IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112

XC68HC12A0CPV8

Manufacturer Part Number
XC68HC12A0CPV8
Description
IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of XC68HC12A0CPV8

Controller Family/series
68HC12
No. Of I/o's
68
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
1
Core Size
16 Bit
Program Memory Size
60KB
Peripherals
ADC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Enhanced Capture Timer
PA3H–PA0H — 8-Bit Pulse Accumulators Holding Registers
MCCNTH/L — Modulus Down-Counter Count Register
Technical Data
258
RESET:
RESET:
$00B6
$00B7
$00B2
$00B3
$00B4
$00B5
BIt 15
BIT 7
Bit 7
BIT 7
BIt 7
BIt 7
Bit 7
Bit 7
1
0
14
6
6
1
6
6
6
6
6
0
Read: any time
Write: has no effect.
These registers are used to latch the value of the corresponding pulse
accumulator when the related bits in register ICPACR ($A8) are enabled
(see
Read: any time
Write: any time
A full access for the counter register should take place in one clock cycle.
A separate read/write for high byte and low byte will give different result
than accessing them as a word.
If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT
register will return the present value of the count register. If the RDMCL
bit is set, reads of the MCCNT will return the contents of the load
register.
Pulse
13
5
5
1
5
5
5
5
5
0
Accumulators).
Enhanced Capture Timer
12
4
4
1
4
4
4
4
4
0
11
3
3
1
3
3
3
3
3
0
10
2
2
1
2
2
2
2
2
0
1
9
1
1
MC68HC912D60A — Rev. 3.1
1
1
1
1
1
0
Freescale Semiconductor
BIT 0
Bit 8
Bit 0
1
BIT 0
Bit 0
Bit 0
Bit 0
Bit 0
0
$00B2–$00B5
$00B6, $00B7
MCCNTH
MCCNTL
PA3H
PA2H
PA1H
PA0H

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