XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 234

• Manufacturer Part Number: XC68HC12A0CPV8
• Description: IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
• Manufacturer: Freescale Semiconductor

Specifications of XC68HC12A0CPV8

• Controller Family/series: 68HC12
• No. Of I/o's: 68
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Core Size: 16 Bit
• Program Memory Size: 60KB
• Peripherals: ADC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Capture Timer
CFORC — Timer Compare Force Register
OC7M — Output Compare 7 Mask Register
Technical Data
234
RESET:
RESET:
OC7M7
FOC7
Bit 7
Bit 7
NOTE:
0
0
OC7M6
FOC6
6
0
6
0
Read anytime but will always return $00 (1 state is transient). Write
anytime.
FOC[7:0] — Force Output Compare Action for Channel 7-0
Read or write anytime.
The bits of OC7M correspond bit-for-bit with the bits of timer port
(PORTT). Setting the OC7Mn will set the corresponding port to be an
output port regardless of the state of the DDRTn bit when the
corresponding IOSn bit is set to be an output compare. This does not
change the state of the DDRT bits. At successful OC7, for each bit that
is set in OC7M, the corresponding data bit OC7D is stored to the
corresponding bit of the timer port.
OC7M has priority over output action on the timer port enabled by OMn
and OLn bits in TCTL1 and TCTL2. If an OC7M bit is set, it prevents the
action of corresponding OM and OL bits on the selected timer port.
A write to this register with the corresponding data bit(s) set causes
the action which is programmed for output compare “n” to occur
immediately. The action taken is the same as if a successful
comparison had just taken place with the TCn register except the
interrupt flag does not get set.
OC7M5
FOC5
5
0
5
0
Enhanced Capture Timer
OC7M4
FOC4
4
0
4
0
OC7M3
FOC3
3
0
3
0
OC7M2
FOC2
2
0
2
0
OC7M1
FOC1
MC68HC912D60A — Rev. 3.1
1
0
1
0
Freescale Semiconductor
OC7M0
FOC0
Bit 0
Bit 0
0
0
$0081
$0082