XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 332

• Manufacturer Part Number: XC68HC12A0CPV8
• Description: IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
• Manufacturer: Freescale Semiconductor

Specifications of XC68HC12A0CPV8

• Controller Family/series: 68HC12
• No. Of I/o's: 68
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Core Size: 16 Bit
• Program Memory Size: 60KB
• Peripherals: ADC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MSCAN Controller
17.13.3 msCAN12 Module Control Register 1 (CMCR1).
Technical Data
332
CMCR1
$0101
RESET
W
R
NOTE:
Bit 7
0
0
LOOPB — Loop Back Self Test Mode
WUPM — Wake-Up Mode
CLKSRC — msCAN12 Clock Source
The CMCR1 register can be written only if the SFTRES bit in CMCR0 is
set.
When this bit is set the msCAN12 performs an internal loop back
which can be used for self test operation: the bit stream output of the
transmitter is fed back to the receiver internally. The RxCAN input pin
is ignored and the TxCAN output goes to the recessive state (1). The
msCAN12 behaves as it does normally when transmitting and treats
its own transmitted message as a message received from a remote
node. In this state the msCAN12 ignores the bit sent during the ACK
slot of the CAN frame acknowledge field to insure proper reception of
its own message. Both transmit and receive interrupts are generated.
This flag defines whether the integrated low-pass filter is applied to
protect the msCAN12 from spurious wake-ups (see
Wake-Up
This flag defines which clock source the msCAN12 module is driven from
(only for system with CGM module; see
6
0
0
0 = Normal operation
1 = Activate loop back self test mode
0 = msCAN12 will wake up the CPU after any recessive to
1 = msCAN12 will wake up the CPU only in the case of dominant pulse
0 = The msCAN12 clock source is EXTALi.
1 = The msCAN12 clock source is SYSCLK, twice the frequency of
dominant edge on the CAN bus.
on the bus which has a length of at least approximately T
ECLK.
Function).
5
0
0
MSCAN Controller
4
0
0
3
0
0
Clock
LOOPB
2
0
MC68HC912D60A — Rev. 3.1
System,
Freescale Semiconductor
WUPM
Programmable
1
0
Figure
17-7).
CLKSRC
wup
Bit 0
0
.