XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 162

IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112

XC68HC12A0CPV8

Manufacturer Part Number
XC68HC12A0CPV8
Description
IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of XC68HC12A0CPV8

Controller Family/series
68HC12
No. Of I/o's
68
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
1
Core Size
16 Bit
Program Memory Size
60KB
Peripherals
ADC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Clock Functions
11.7 System Clock Frequency formulas
11.8 Clock Divider Chains
Technical Data
162
NOTE:
See
SLWCLK = EXTALi / ( 2 x SLOW )
SLWCLK = EXTALi
PLLCLK = 2 x EXTALi x (SYNR + 1) / (REFDV + 1)
ECLK = SYSCLK / 2
XCLK = SLWCLK / 2
PCLK = SYSCLK / 2
BCLK
Boolean equations:
SYSCLK = (BCSP & PLLCLK) | (BCSP & BCSS & EXTALi) | (BCSP &
BCSS & SLWCLK)
MCLK = (PCLK & MCS) | (XCLK & MCS)
MSCAN system = (EXTALi & CLKSRC) | (SYSCLK & CLKSRC)
BDM system = (BCLK & CLKSW) | (ECLK & CLKSW)
During limp-home mode PCLK, ECLK, BCLK, MCLK and XCLK are
supplied by VCO (PLLCLK).
Figure
clock divider chains for the various peripherals on the
MC68HC912D60A.
1. If SYSCLK is slower than EXTALi (BCSS=1, BCSP=0, SLOW>0), BCLK becomes ECLK.
Figure
(1)
11-6,
= EXTALi / 2
11-6:
Figure
Clock Functions
11-7,
Figure
11-8, and
Figure 11-9
MC68HC912D60A — Rev. 3.1
SLOW = 1,2,..63
SLOW = 0
Freescale Semiconductor
summarize the

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