XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 266

IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112

XC68HC12A0CPV8

Manufacturer Part Number
XC68HC12A0CPV8
Description
IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of XC68HC12A0CPV8

Controller Family/series
68HC12
No. Of I/o's
68
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
1
Core Size
16 Bit
Program Memory Size
60KB
Peripherals
ADC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Multiple Serial Interface
15.4.1 Data Format
15.4.2 SCI Baud Rate Generation
Technical Data
266
The serial data format requires the following conditions:
The basis of the SCI baud rate generator is a 13-bit modulus counter.
This counter gives the generator the flexibility necessary to achieve a
reasonable level of independence from the CPU operating frequency
and still be able to produce standard baud rates with a minimal amount
of error. The clock source for the generator comes from the M Clock.
An idle-line in the high state before transmission or reception of a
message.
A start bit (logic zero), transmitted or received, that indicates the
start of each character.
Data that is transmitted or received least significant bit (LSB) first.
A stop bit (logic one), used to indicate the end of a frame. (A frame
consists of a start bit, a character of eight or nine data bits and a
stop bit.)
A BREAK is defined as the transmission or reception of a logic
zero for one frame or more.
This SCI supports hardware parity for transmit and receive.
SCI Baud Rate
Multiple Serial Interface
Desired
Table 15-1. Baud Rate Generation
14400
19200
38400
1200
2400
4800
9600
110
300
600
BR Divisor for
M = 4.0 MHz
2273
833
417
208
104
52
26
17
13
BR Divisor for
M = 8.0 MHz
MC68HC912D60A — Rev. 3.1
4545
2273
833
417
208
104
52
35
26
13
Freescale Semiconductor

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