XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 453

• Manufacturer Part Number: XC68HC12A0CPV8
• Description: IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
• Manufacturer: Freescale Semiconductor

Specifications of XC68HC12A0CPV8

• Controller Family/series: 68HC12
• No. Of I/o's: 68
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Core Size: 16 Bit
• Program Memory Size: 60KB
• Peripherals: ADC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

operand — Data on which an operation is performed. Usually a statement consists of an
oscillator — A circuit that produces a constant frequency square wave that is used by the
OTPROM — One-time programmable read-only memory. A nonvolatile type of memory that
overflow — A quantity that is too large to be contained in one byte or one word.
page zero — The first 256 bytes of memory (addresses $0000–$00FF).
parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted.
PC — See “program counter (PC).”
peripheral — A circuit not under direct CPU control.
phase-locked loop (PLL) — A clock generator circuit in which a voltage controlled oscillator
PLL — See "phase-locked loop (PLL)."
pointer — Pointer register. An index register is sometimes called a pointer register because its
polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different
polling — Periodically reading a status bit to monitor the condition of a peripheral device.
port — A set of wires for communicating with off-chip devices.
prescaler — A circuit that generates an output signal related to the input signal by a fractional
program — A set of computer instructions that cause a computer to perform a desired operation
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
operator and an operand. For example, the operator may be an add instruction, and the
operand may be the quantity to be added.
computer as a timing and sequencing reference.
cannot be reprogrammed.
In a system that uses odd parity, every byte is expected to have an odd number of logic
1s. In an even parity system, every byte should have an even number of logic 1s. In the
transmitter, a parity generator appends an extra bit to each byte to make the number of
logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts
the number of logic 1s in each byte. The parity checker generates an error signal if it finds
a byte with an incorrect number of logic 1s.
produces an oscillation which is synchronized to a reference signal.
contents are used in the calculation of the address of an operand, and therefore points to
the operand.
voltage levels, V
scale factor such as 1/2, 1/8, 1/10 etc.
or operations.
DD
and V
SS
.
Glossary
Technical Data
Glossary
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