AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 34

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9547
During any given PFD phase error sample, the detector either adds
water with the fill bucket or removes water with the drain bucket
(one or the other but not both). The decision on whether to add or
remove water depends on the threshold level specified by the user.
The phase lock threshold value is a 16-bit number stored in the
profile registers and carries units of picoseconds (ps). Thus, the
phase lock threshold extends from 0 ns to ±65.535 ns and repre-
sents the magnitude of the phase error at the output of the PFD.
The phase lock detector compares each phase error sample at the
output of the PFD to the programmed phase threshold value. If the
absolute value of the phase error sample is less than or equal to
the programmed phase threshold value, the detector control logic
dumps one fill bucket into the tub. Otherwise, it removes one
drain bucket from the tub. Note that it is not the polarity of the
phase error sample but, rather, its magnitude relative to the phase
threshold value that determines whether to fill or drain. If more
filling is taking place than draining, the water level in the tub
eventually rises above the high water mark (+1024), which causes
the phase lock detector to indicate lock. If more draining is taking
place than filling, the water level in the tub eventually falls below
the low water mark (−1024), which causes the phase lock detector
to indicate unlock. The ability to specify the threshold level, fill
rate, and drain rate enables the user to tailor the operation of
the phase lock detector to the statistics of the timing jitter
associated with the input reference signal.
Note that when the AD9547 enters the free-run or holdover
mode, the DPLL phase lock detector indicates unlocked. Also,
when the AD9547 performs a reference switchover, the state of
the lock detector prior to the switch is preserved during the
transition period.
DPLL Frequency Lock Detector
The operation of the frequency lock detector is identical to that
of the phase lock detector. The only difference is that the fill or
drain decision is based on the period deviation between the
reference and feedback signals of the DPLL instead of the phase
error at the output of the PFD.
The frequency lock detector uses a 24-bit frequency threshold
register specified in units of picoseconds (ps). Thus, the fre-
quency threshold value extends from 0 μs to ±16.777215 μs.
TUNING WORD
FREQUENCY
(FTW)
48
48-BIT ACCUMULATOR
48
48
D
Q
Figure 40. DDS Block Diagram
Rev. B | Page 34 of 104
19
OFFSET
16
PHASE
19
It represents the magnitude of the difference in period between
the reference and feedback signals at the input to the DPLL. For
example, if the reference signal is 1.25 MHz and the feedback
signal is 1.38 MHz, the period difference is approximately 75.36 ns
(|1/1,250,000 − 1/1,380,000| ≈ 75.36 ns).
DIRECT DIGITAL SYNTHESIZER (DDS)
DDS Overview
One of the primary building blocks of the digital PLL is a direct
digital synthesizer (DDS). The DDS behaves like a sinusoidal
signal generator. The frequency of the sinusoid generated by the
DDS is determined by a frequency tuning word (FTW), which
is a digital (that is, numeric) value. Unlike an analog sinusoidal
generator, a DDS uses digital building blocks and operates as a
sampled system. Thus, it requires a sampling clock (f
as the fundamental timing source of the DDS. The accumulator
behaves as a modulo-2
(FTW). A block diagram of the DDS appears in Figure 40.
The input to the DDS is the 48-bit FTW. The FTW serves as
a step size value. On each cycle of f
value of the FTW to the running total at its output. For example,
given that FTW = 5, the accumulator counts by fives, incre-
menting on each f
the upper end of its capacity (2
it rolls over but retains the excess. The average rate at which the
accumulator rolls over establishes the frequency of the output
sinusoid. The average rollover rate of the accumulator establishes
the output frequency (f
Solving this equation for FTW yields
For example, given that f
FTW = 43,774,988,378,041 (0x27D028A1DFB9).
Note that the minimum DAC output frequency is 62.5 MHz;
therefore, normal operation requires an FTW that yields an
output frequency in excess of this lower bound.
CONVERSION
AMPLITUDE
ANGLE TO
FTW
f
DDS
=
=
⎛
⎜
⎝
round
FTW
2
14
48
S
cycle. Over time, the accumulator reaches
⎡
⎢
⎢
⎣
⎞
⎟
⎠
2
DDS
f
48
48
S
(14-BIT)
counter with a programmable step size
⎛
⎜
⎜
⎝
) of the DDS and is given by
S
DAC
= 1 GHz and f
f
DDS
f
S
48
f
⎞
⎟
⎟
⎠
S
⎤
⎥
⎥
⎦
in this case), at which point,
S
, the accumulator adds the
DAC+
DAC–
DDS
= 155.52 MHz, then
S
) that serves