AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 70

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9547
Register 0x0209 to Register 0x0210—IRQ Mask
The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (Address 0x0D02 to Address 0x0D09).
When set to Logic 1, the IRQ mask bits enable the corresponding IRQ monitor bits to indicate an IRQ event. The default for all IRQ mask
bits is Logic 0, which prevents the IRQ monitor from detecting any internal interrupts.
Table 50. IRQ Mask for SYSCLK
Address
0x0209
Table 51. IRQ Mask for Distribution Sync, Watchdog Timer, and EEPROM
Address
0x020A
Table 52. IRQ Mask for the Digital PLL
Address
0x020B
Table 53. IRQ Mask for History Update, Frequency Limit, and Phase Slew Limit
Address
0x020C
Bit
[7:6]
5
4
[3:2]
1
0
Bit
[7:4]
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit
[7:5]
4
3
2
1
0
Bit Name
Unused
SYSCLK unlocked
SYSCLK locked
Unused
SYSCLK cal complete
SYSCLK cal started
Bit Name
Unused
Distribution sync
Watchdog timer
EEPROM fault
EEPROM complete
Bit Name
Switching
Closed
Free run
Holdover
Frequency unlocked
Frequency locked
Phase unlocked
Phase locked
Bit Name
Unused
History updated
Frequency unclamped
Frequency clamped
Phase slew unlimited
Phase slew limited
Description
Unused.
Enables IRQ for indicating a SYSCLK PLL state transition from locked to unlocked.
Enables IRQ for indicating a SYSCLK PLL state transition from unlocked to locked.
Unused.
Enables IRQ for indicating that SYSCLK calibration is complete.
Enables IRQ for indicating that SYSCLK calibration has begun.
Description
Unused.
Enables IRQ for indicating a distribution sync event.
Enables IRQ for indicating expiration of the watchdog timer.
Enables IRQ for indicating a fault during an EEPROM load or save operation.
Enables IRQ for indicating successful completion of an EEPROM load or save operation.
Description
Enables IRQ for indicating that the DPLL is switching to a new reference.
Enables IRQ for indicating that the DPLL has entered closed-loop operation.
Enables IRQ for indicating that the DPLL has entered free-run mode.
Enables IRQ for indicating that the DPLL has entered holdover mode.
Enables IRQ for indicating that the DPLL lost frequency lock.
Enables IRQ for indicating that the DPLL has acquired frequency lock.
Enables IRQ for indicating that the DPLL lost phase lock.
Enables IRQ for indicating that the DPLL has acquired phase lock.
Description
Unused.
Enables IRQ for indicating the occurrence of a tuning word history update.
Enables IRQ for indicating a state transition of the frequency limiter from clamped to
unclamped.
Enables IRQ for indicating a state transition of the frequency limiter from unclamped to
clamped.
Enables IRQ for indicating a state transition of the phase slew limiter from slew limiting to
not slew limiting.
Enables IRQ for indicating a state transition of the phase slew limiter from not slew
limiting to slew limiting.
Rev. B | Page 70 of 104