AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 35

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDS Phase Offset
The relative phase of the sinusoid generated by the DDS is numer-
ically controlled by adding a phase offset word to the output of the
DDS accumulator. This is accomplished via the open loop phase
offset register (Address 0x030D to Address 0x030E), which is a
programmable 16-bit value (Δphase). The resulting phase offset,
ΔΦ (radians), is given by
Phase offset and relative time offset are directly related. The
time offset is (Δphase/2
output frequency of the DDS (Hz).
DAC Output
The output of the digital core of the DDS is a time series of
numbers representing a sinusoidal waveform. The DAC
translates the numeric values to an analog signal. The DAC
output signal appears at two pins that constitute a balanced
current source architecture (see Figure 41).
The value of I
current word in the DAC current register (Address 0x0213 and
Address 0x0214). The value of the 10-bit word (I
according to the following formula:
TUNING WORD PROCESSING
The frequency tuning words that dictate the output frequency
of the DDS come from one of three sources (see Figure 42).
•
•
•
I
The free-running frequency tuning word register
The output of the digital loop filter
The output of the tuning word history processor
Δ
FS
Φ
DACOUTP
= 120 μA × (72 +
I
FS
=
2
2
CODE
14
π
I
SCALE
FS
⎛ Δ
⎜
⎝
– 1
is programmable via the 10-bit DAC full-scale
13
phase
2
GND
50Ω
16
10
Figure 41. DAC Output Pins
⎞
⎟
⎠
16
)/f
⎛
⎜
⎝
CURRENT
CONTROL
CURRENT
16
DDS
MIRROR
SWITCH
SWITCH
ARRAY
14
3
AVDD3
CODE
16
⎞
⎟
⎠
(seconds), where f
× I
I
FS
SCALE
)
GND
50Ω
14
I
FS
DACOUTN
1–
SCALE
DDS
2
CODE
14
– 1
is the
) sets I
FS
Rev. B | Page 35 of 104
When the DPLL is in free-run mode, the DDS tuning word
is the value stored in the free-running frequency tuning word
register (Address 0x0300 to Address 0x0305). When the DPLL
is operating normally (closed loop), the DDS tuning word comes
from the output of the digital loop filter, which changes dynami-
cally to maintain phase lock with the input reference signal
(assuming that the device has not performed an automatic switch
to holdover mode). When the DPLL is in holdover mode, the DDS
tuning word depends on a historical record of past tuning words
during the time that the DPLL operated in closed-loop mode.
However, regardless of the operating mode, the DDS output
frequency is ultimately subject to the boundary conditions
imposed by the frequency clamp logic as explained in the
Frequency Clamp section.
Frequency Clamp
The user controls the frequency clamp boundaries via the pull-
in range limit registers (Address 0x0307 to Address 0x030C).
These registers allow the user to fix the DDS output frequency
between an upper and lower bound with a granularity of 24 bits.
Note that these upper and lower bounds apply regardless of the
frequency tuning word that appears at the input to the DDS.
The register value relates to the absolute upper or lower
frequency bound (f
where N is the value stored in the upper- or lower-limit register,
and f
Even though the frequency clamp limits put a bound on the
DDS output frequency, the DPLL is still free to steer the DDS
frequency within the clamp limits. The default register values
set the clamp range from 0 Hz (dc) to f
the frequency clamp functionality until the user alters the
register values.
Frequency Tuning Word History
The AD9547 has the ability to track the history of the tuning
word samples generated by the DPLL digital loop filter output.
It does so by periodically computing the average tuning word
value over a user-specified interval. The user programs the
interval via the 24-bit history accumulation timer register
(Address 0x0318 to Address 0x031A). This 24-bit value repre-
sents a time interval (T
extends from 1 ms to a maximum of 4:39:37.215 (hr:min:sec).
TUNING WORD
TUNING WORD
TUNING WORD
f
FROM DIGITAL
S
CLAMP
FREE-RUN
LOOP FILTER
HISTORY
is the system sample rate.
UPDATE
= f
S
× ( N /2
Figure 42. Tuning Word Processing
CLAMP
CONTROL
24
ROUTING
TUNING
WORD
)
AVG
) as
) in units of milliseconds (ms) that
TUNING
LOWER
WORD
TUNING WORD
PROCESSOR
HISTORY
TUNING
CLAMP
WORD
S
, effectively eliminating
TUNING
UPPER
WORD
AD9547
TO DDS