AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 42

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9547
The synchronization event is the clearing operation; that is, the
Logic 1 to Logic 0 transition of the bit.
The primary synchronization signal can synchronize the distri-
bution output directly, or it can enable a secondary synchronization
signal. This functionality depends on the two sync source bits
in the distribution synchronization register (Register 0x0402,
Bits[5:4]).
When sync source = 00 (direct), the falling edge of the primary
synchronization signal directly synchronizes the distribution
output.
When sync source = 01, the rising edge of the primary synchroni-
zation signal triggers the circuitry that detects a rising edge of the
active input reference. The detection of the rising edge synchro-
nizes the distribution output.
When sync source = 10, the rising edge of the primary synchro-
nization signal triggers the circuitry that detects a rollover of the
DDS accumulator (after processing by the DPLL feedback divider).
This corresponds to the zero crossing of the output of the phase-to-
amplitude converter in the DDS (less the open-loop phase offset
stored in Register 0x030D and Register 0x030E). The detection
of the DPLL feedback edge synchronizes the distribution output.
Active Reference Synchronization (Zero Delay)
Active reference synchronization is the term applied to the case
when sync source = 01 (Register 0x0402, Bits[5:4]). Referring to
Figure 46, this means that the active reference sync path is active
because Bit 4 = 1, enabling the lower AND gate and disabling
the upper AND gate. The edge detector in the active reference
sync block monitors the rising edges of the active reference
(the mux selects the active reference automatically). The edge
(ADDRESS DX 0x0A02[1])
(REGISTER DX 0x0403)
MULTIFUNCTION PIN
AUTOMATIC SYNC
SYNC SOURCE
EEPROM SYNC
DIRECT SYNC
SOURCE
SOURCE
SOURCE
SYNCHRONIZATION
PRIMARY
SIGNAL
FEEDBACK
Figure 46. Output Synchronization Block Diagram
DETECT
EDGE
DPLL
EDGE
DPLL EDGE SYNC
DIRECT SYNC
Rev. B | Page 42 of 104
ARM
SYSCLK/4
DETECT
EDGE
REGISTER
0x0402[4]
REGISTER
detector is armed via the primary synchronization signal, which
is one of the four inputs to the OR gate (typically the direct sync
source). As soon as the edge detector is armed, its output goes high,
which stalls the output dividers in the clock distribution block.
Furthermore, once armed, a rising edge from the active reference
forces the output of the edge detector low. This restarts the output
dividers, thereby synchronizing the clock distribution block.
The term zero delay applies because it provides a means to edge-
align the output signal with the active input reference signal.
Typically, zero-delay architectures use the output signal in the
feedback loop of a PLL to track input/output edge alignment.
Active reference synchronization, however, operates open loop.
That is, synchronization of the output via the distribution
synchronization logic occurs on a single edge of the active
reference.
The fact that an active reference edge triggers the falling edge of
the synchronization pulse means that the falling edge is asynchro-
nous to the signal that clocks the distribution output dividers
(CLKINx). Therefore, the output clock distribution logic reclocks
the internal synchronization pulse to synchronize it with the
CLKINx signal. This means that the output dividers restart after
a deterministic delay associated with the reclocking circuitry.
This deterministic delay has two components. The first deter-
ministic delay component is four or five periods of the CLKINx
signal. The one period uncertainty is due to the unknown position
of the asynchronous reference clock edge relative to the CLKINx
signal. The second deterministic delay component is one output
period of the distribution divider.
0x0402[5]
REF BB
ACTIVE REFERENCE SYNC
REF A
0
1
ARM
RESET
DETECT
EDGE
TO MULTIFUNCTION
PIN STATUS LOGIC
DIVIDERS
STALL
TO CLOCK
DISTRIBUTION
SYNCHRONIZATION
CONTROL
SYNC OUTPUT
DISTRIBUTION