AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 5

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LOGIC INPUTS (M0 TO M7, RESET)
Table 4.
Parameter
INPUT VOLTAGE
INPUT CURRENT (I
INPUT CAPACITANCE (C
LOGIC OUTPUTS (M0 TO M7, IRQ)
Table 5.
Parameter
OUTPUT VOLTAGE
IRQ LEAKAGE CURRENT
SYSTEM CLOCK INPUTS (SYSCLKP, SYSCLKN)
Table 6.
Parameter
SYSTEM CLOCK PLL BYPASSED
SYSTEM CLOCK PLL ENABLED
Input High Voltage (V
Input Low Voltage (V
Output High Voltage (V
Output Low Voltage (V
Active Low Output Mode
Active High Output Mode
Input Frequency Range
Minimum Input Slew Rate
Duty Cycle
Common-Mode Voltage
Differential Input Voltage Sensitivity
Input Capacitance
Input Resistance
PLL Output Frequency Range
Phase Frequency Detector (PFD) Rate
Frequency Multiplication Range
VCO Gain
High Frequency Path
Input Frequency Range
Minimum Input Slew Rate
Frequency Divider Range
Common-Mode Voltage
Differential Input Voltage Sensitivity
Input Capacitance
Input Resistance
INH
, I
INL
IL
IN
)
IH
)
)
OL
)
OH
)
)
Min
2.1
Min
2.7
Min
500
1000
40
100
900
6
100.1
200
1
100
Typ
±80
3
Typ
Typ
1.2
2
2.5
70
1
3
2.5
Rev. B | Page 5 of 104
Max
0.8
±200
Max
0.4
1
1
Max
1000
60
1000
150
255
500
8
Unit
V
V
μA
pF
Unit
V
V
μA
μA
Unit
MHz
V/μs
%
V
mV p-p
pF
kΩ
MHz
MHz
MHz/V
MHz
V/μs
V
mV p-p
pF
kΩ
Test Conditions/Comments
Test Conditions/Comments
I
I
Open-drain mode
V
V
OH
OL
Test Conditions/Comments
Minimum limit imposed for jitter performance
Internally generated
Minimum voltage across pins is required to ensure
switching between logic states; the instantaneous
voltage on either pin must not exceed the supply rails;
ac ground the unused input to accommodate single-
ended operation
Single-ended, each pin
Assumes valid system clock and PFD rates
Minimum limit imposed for jitter performance
Binary steps (M = 1, 2, 4, 8)
Internally generated
This is the minimum voltage required across the pins to
ensure switching between logic states; the
instantaneous voltage on either pin must not exceed
the supply rails; ac ground the unused input to
accommodate single-ended operation
Single-ended, each pin
OH
OL
= 1 mA
= 1 mA
= 0 V
= 3.3 V
AD9547