AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 72

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9547
DPLL CONFIGURATION (REGISTER 0x0300 TO REGISTER 0x031B)
Table 57. Free-Running Frequency Tuning Word
Address
0x0300
0x0301
0x0302
0x0303
0x0304
0x0305
1
Table 58. Update TW
Address
0x0306
Table 59. Pull-in Range Lower and Upper Limit
Address
0x0307
0x0308
0x0309
0x030A
0x030B
0x030C
1
Table 60. Open-Loop Phase Offset
Address
0x030D
0x030E
1
Table 61. Fixed Closed-Loop Phase Lock Offset
Address
0x030F
0x0310
0x0311
0x0312
0x0313
1
The default free-running tuning word is 0x000000 = 0, which equates to 0 Hz.
The default pull-in range lower limit is 0 and the upper range limit is 0xFFFFFF, which effectively spans the full output frequency range of the DDS.
The default DDS phase offset is 0.
The default fixed closed loop phase lock offset is 0.
Bit
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit
[7:1]
0
Bit
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit
[7:0]
[7:0]
Bit
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
Free-running frequency tuning word
(expressed as a 48-bit frequency
tuning word)
Unused
Bit Name
Pull-in range lower limit (expressed
as a 24-bit frequency tuning word)
Pull-in range upper limit (expressed
as a 24-bit frequency tuning word)
Bit Name
Open-loop phase offset
(expressed in units of π/2
Bit Name
Fixed phase lock offset
(expressed in ps)
Bit Name
Update TW
1
15
radians)
1
1
1
Rev. B | Page 72 of 104
Description
Free-running frequency tuning word, Bits[7:0].
Free-running frequency tuning word, Bits[15:8].
Free-running frequency tuning word, Bits[23:16].
Free-running frequency tuning word, Bits[31:24].
Free-running frequency tuning word, Bits[39:32].
Free-running frequency tuning word, Bits[47:40].
Description
Unused.
A Logic 1 written to this bit transfers the free-running frequency tuning word
(Register 0x0300 to Register 0x0305) to the register embedded in the tuning
word processing logic. Note that it is not necessary to write the update TW bit
when the device is in free-run mode. This is an autoclearing bit.
Description
Lower limit pull-in range, Bits[7:0].
Lower limit pull-in range, Bits[15:8].
Lower limit pull-in range, Bits[23:16].
Upper limit pull-in range, Bits[7:0].
Upper limit pull-in range, Bits[15:8].
Upper limit pull-in range, Bits[23:16].
Description
DDS phase offset, Bits[7:0].
DDS phase offset, Bits[15:8].
Description
Fixed phase lock offset, Bits[7:0].
Fixed phase lock offset, Bits[15:8].
Fixed phase lock offset, Bits[23:16].
Fixed phase lock offset, Bits[31:24].
Fixed phase lock offset, Bits[39:32].