AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 36

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9547
Note that history accumulation timer = 0 should not be pro-
grammed because it may cause improper device operation.
The control logic performs a calculation of the average tuning
word during the T
history register (Address 0x0D14 to Address 0x0D19). Compu-
tation of the average for each T
previous interval (that is, the average is a memoryless average as
opposed to a true moving average). In addition, at the end of each
T
strobe pulse sets the history updated bit in the IRQ monitor
register (assuming that the bit is enabled via the IRQ mask register).
Furthermore, the strobe pulse is available as an output signal via
the multifunction pins (see the Multifunction Pins (M0 to M7)
section).
History accumulation begins when the device switches to a new
reference. By default, the device clears any previous history when
it switches to a new reference. Furthermore, the user can clear
the tuning word history under software control using Bit 2 of
Register 0x0A03 or under hardware control via the multifunction
pins (see the Multifunction Pins (M0 to M7) section). However,
the user has the option of programming the device to retain
(rather than clear) the old history by setting the persistent
history bit (Register 0x031B, Bit 3).
When the tuning word history is nonexistent (that is, after
a power-up, reset, or switchover to a new reference with the
persistent history bit cleared), the device waits for the history
accumulation timer (T
history value in the holdover history register.
In cases where T
problem arises in that the first averaged result does not become
available until the full T
that as much as 4½ hours can elapse before the first averaged
result is available. If the device must switch to holdover during
this time, a tuning word history is not available.
To alleviate this problem, the user can access the incremental
average bits in the history mode register (Register 0x031B,
Bits[2:0]). If the history has been cleared, this 3-bit value, K
(0 ≤ K ≤ 7), specifies the number of intermediate averages to take
during the first, and only the first, T
intermediate averages are calculated; therefore, the first average
occurs after Interval T
if K = 4, for example, four intermediate averages are taken during
the first T
These average computations occur at T
T
of powers of 2 beginning with T
mediate averages occurs only during the first T
subsequent average computations occur at evenly spaced
intervals of T
AVG
AVG
/2, and T
interval, the device generates an internal strobe pulse. The
AVG
interval.
AVG
AVG
AVG
.
(note that the denominator exhibits a sequence
AVG
is quite large (4½ hours, for example), a
interval and stores the result in the holdover
AVG
AVG
AVG
(the default operating mode). However,
) to expire before storing the first
interval passes. Thus, it is possible
AVG
AVG
interval is independent of the
AVG
/2
K
interval. When K = 0, no
). The calculation of inter-
AVG
/16, T
AVG
AVG
interval. All
/8, T
AVG
/4,
Rev. B | Page 36 of 104
LOOP CONTROL STATE MACHINE
The loop control state machine is responsible for monitoring,
initiating, and sequencing changes to the DPLL loop. Generally,
it automatically controls the transition between input references
and the entry and exit of holdover mode. In controlling loop state
changes, the state machine also arbitrates the application of new
loop filter coefficients, divider settings, and phase detector offsets
based on the profile settings. The user can manually force the
device into holdover or free-run mode via the loop mode register
(Address 0x0A01), as well as force the selection of a specific
input reference.
Switchover
Switchover occurs when the loop controller switches directly
from one input reference to another. Functionally, the AD9547
handles a reference switchover by briefly entering holdover mode
then immediately recovering. During the switchover event,
however, the AD9547 preserves the status of the lock detectors
in order to avoid phantom unlock indications.
Holdover
The holdover state of the DPLL is an open-loop operating mode;
that is, the device no longer operates as a closed-loop system.
Instead, the output frequency remains constant and is dependent
on the device programming and availability of the tuning word
history as explained in the following paragraphs.
If a tuning word history exists (see the Frequency Tuning Word
History section), the holdover frequency is the average frequency
just prior to entering the holdover state. If there is no tuning word
history, the holdover frequency depends on the state of the single
sample fallback bit in the history mode register (Register 0x031B,
Bit 4). If the single sample fallback bit is Logic 0, the holdover
frequency is the frequency defined in the free-running frequency
tuning word register (Address 0x0300 to Address 0x0305). If the
single sample fallback bit is Logic 1, the holdover frequency is the
last instantaneous frequency output by the DDS just prior to the
device entering holdover mode (note that this is not the average
frequency prior to holdover).
The initial holdover frequency accuracy depends on the loop
bandwidth of the DPLL and the time elapsed to compute a tuning
word history. The longer the historical average, the more accurate
the initial holdover frequency (assuming a drift-free system clock).
Furthermore, the stability of the system clock establishes the
stability and long-term accuracy of the holdover output frequency.
Another consideration is the 48-bit frequency tuning resolution
of the DDS and its relationship to fractional frequency error, Δf
In this equation, f
is the DDS output frequency. The worst-case scenario is maximum
f
2.8 × 10
S
(1 GHz) and minimum f
Δ
f
f
O
O
−14
, which is less than one part in ten trillion.
=
2
49
f
S
f
O
S
is the sample rate of the output DAC and f
O
(62.5 MHz), which yields Δf
O
/f
O
O
=
/f
O
O
.