AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 55

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Transfer Process
The master initiates data transfer by asserting a start condition.
This indicates that a data stream follows. All I2C slave devices
connected to the serial bus respond to the start condition.
The master then sends an 8-bit address byte over the SDA line,
consisting of a 7-bit slave address (MSB first) plus an R/ W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 =
write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by sending an acknowledge bit. All other devices
on the bus remain idle while the selected device waits for data to be
read from or written to it. If the R/ W bit = 0, the master (trans-
mitter) writes to the slave device (receiver). If the R/ W bit = 1,
the master (receiver) reads from the slave device (transmitter).
See the
Data is then sent over the serial bus in the format of nine clock
pulses, one data byte (eight bits) from either master (write mode)
or slave (read mode) followed by an acknowledge bit from the
receiving device. The number of bytes that can be transmitted
per transfer is unrestricted. In write mode, the first two data
Data Transfer Format
In write byte format, the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.
In send byte format, the send byte protocol is used to set up the register address for subsequent reads.
In receive byte format, the receive byte protocol is used to read the data bytes from RAM starting from the current address.
Read byte format combines the format of the send byte and the receive byte formats.
S
S
S
S
Address
Address
Slave
Data Transfer Format
Slave
SDA
SCL
SDA
SCL
Slave Address
Slave Address
S
S
W
W
A
A
MSB
1
1
High Byte
Address
section for the command format.
RAM
Figure 60. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration)
Figure 61. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration)
W
RAM Address
R
High Byte
2
2
A
A
A
3 TO 7
3 TO 7
Low Byte
Address
RAM Data 0
RAM
RAM Address High Byte
A
8
8
MASTER RECEIVER
RAM Address
SLAVE RECEIVER
Rev. B | Page 55 of 104
A
Low Byte
ACK FROM
ACK FROM
9
9
Sr
A
Address
bytes immediately after the slave address byte are the internal
memory (control registers) address bytes with the high address
byte first. This addressing scheme gives a memory address up to
2
bytes are register data written into or read from the control regi-
sters. In read mode, the data bytes after the slave address byte are
register data written into or read from the control registers.
When all data bytes are read or written, stop conditions are estab-
lished. In write mode, the master (transmitter) asserts a stop
condition to end data transfer during the 10
the acknowledge bit for the last data byte from the slave device
(receiver). In read mode, the master device (receiver) receives the
last data byte from the slave device (transmitter) but does not pull
SDA low during the ninth clock pulse. This is known as a no
acknowledge bit. When receiving the no acknowledge bit, the slave
device knows the data transfer is finished and enters idle mode.
The master then takes the data line low during the low period
before the 10
to assert a stop condition.
A start condition can be used in place of a stop condition.
Furthermore, a start or stop condition can occur at any time,
and partially transferred bytes are discarded.
Slave
1
16
1
− 1 = 65,535. The data bytes after these two memory address
A
RAM Data 1
2
2
Data 0
A
R
RAM
th
clock pulse, and high during the 10
A
3 TO 7
3 TO 7
RAM
Data
RAM Address Low Byte
A
0
A
Data 1
RAM
A
8
MASTER RECEIVER
8
SLAVE RECEIVER
NO ACK FROM
RAM Data 2
RAM
Data
ACK FROM
1
9
A
9
th
clock pulse following
A
Data 2
RAM
10
P
10
P
RAM
Data
th
2
clock pulse
AD9547
A
A
A
A
P
P
P
P