AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 54

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9547
I²C SERIAL PORT OPERATION
The I
control pins and is a de facto standard throughout the I
industry. However, its disadvantage is programming speed,
which is 400 kbps maximum. The AD9547 I2C port design is
based on the I2C fast mode standard from Philips, so it supports
both the 100 kHz standard mode and the 400 kHz fast mode.
Fast mode imposes a glitch tolerance requirement on the control
signals; that is, the input receivers ignore pulses of less than
50 ns duration.
The AD9547 I2C port consists of a serial data line (SDA) and
a serial clock line (SCL). In an I2C bus system, the AD9547 is
connected to the serial bus (data bus SDA and clock bus SCL)
as a slave device; that is, no clock is generated by the AD9547.
The AD9547 uses direct 16-bit memory addressing instead of
traditional 8-bit memory addressing.
The AD9547 allows for up to seven unique slave devices to occupy
the I
transmitted as part of an I
ing slave address responds to subsequent I
device slave address is 1001xxx (the last three bits are determined
by the M0 to M2 pins). The four MSBs (1001) are hardwired,
whereas the three LSBs (xxx, determined by the M0 to M2 pins)
are programmable via the power-up state of the multifunction
pins (see the Initial M0 to M7 Pin Programming section).
I
A summary of the various I
Table 34. I
Abbreviation
S
Sr
P
A
A
W
R
2
C Bus Characteristics
2
2
C bus. These are accessed via a 7-bit slave address that is
C interface has the advantage of requiring only two
SDA
SCL
2
C Bus Abbreviation Definitions
S
2
C packet. Only the device with a match-
MSB
2
1
C protocols appears in Table 34.
Definition
Start
Repeated start
Stop
Acknowledge
No acknowledge
Write
Read
2
2
C commands. The
3 TO 7
2
C
8
Figure 59. Acknowledge Bit
SLAVE RECEIVER
Rev. B | Page 54 of 104
ACK FROM
9
SDA
The transfer of data appears graphically in Figure 57. One clo
pulse is generated for each data bit transferred. The data on the
SDA line must be stable during the
The high or low state of the data line can change only when the
clock signal on the SCL line is low.
SCL
Start/stop functionality appears graphically in Figure 58. The
start condition is characterized by a high-to-low transition o
the SDA line while SCL is high. The start condition is always
generated by the master to initialize data transfer. The stop
condition is characterized by a low-to-high transitio
SDA line while SCL is high. The stop condition is always
generated by the master to terminate data transfer.
Every byte on the SDA line must be eight bits long. Each byte
must be followed by an acknowledge bit. Bytes are sent MSB first.
The acknowledge bit (A) is the ninth bit attached to any 8-bit
data byte. An acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter tha
byte has been received. It is done by pulling the SDA line low
during the ninth clock pulse after each 8-bit data byte.
The no acknowledge bit ( A ) is the ninth bit attached to any 8-bit
data byte. A no acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has not been received. It is done by leaving the SDA line
high during the ninth clock pulse after each 8-bit data byte.
1
SDA
SCL
START CONDITION
2
S
DATA VALID
DATA
Figure 58. Start and Stop Condition
STA
3 TO 7
BLE;
Figure 57. Valid Bit Transfer
LINE
ALLOWED
CHANGE
OF DATA
8
SLAVE RECEIVER
high period of the clock.
ACK FROM
9
STOP CONDITION
10
P
n on the
P
t the
n
ck