AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 93

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 137. IRQ Monitor for History Update, Frequency Limit, and Phase Slew Limit
Address
0x0D05
Table 138. IRQ Monitor for Reference Inputs
Address
0x0D06
0x0D07
0x0D08
0x0D09
Table 139. DPLL Status
Address
0x0D0A
0x0D0B
Bit
[7:5]
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
[7:0]
[7:0]
Bit
7
6
5
4
3
2
1
0
7
6
[5:3]
2
[1:0]
Bit Name
Unused
History updated
Frequency unclamped
Frequency clamped
Phase slew unlimited
Phase slew limited
Bit Name
Ref AA new profile
Ref AA validated
Ref AA fault cleared
Ref AA fault
Ref A new profile
Ref A validated
Ref A fault cleared
Ref A fault
Ref BB new profile
Ref BB validated
Ref BB fault cleared
Ref BB fault
Ref B new profile
Ref B validated
Ref B fault cleared
Ref B fault
Unused
Bit Name
Offset slew limiting
Phase build-out
Frequency lock
Phase lock
Loop switching
Holdover
Active
Free running
Frequency clamped
History available
Active reference priority
Unused
Active reference
Description
Unused.
Indicates the occurrence of a tuning word history update.
Indicates a frequency limiter state transition from clamped to unclamped.
Indicates a frequency limiter state transition from unclamped to clamped.
Indicates a phase slew limiter state transition from slew limiting to not slew limiting.
Indicates a phase slew limiter state transition from not slew limiting to slew limiting.
Description
Indicates that Ref AA has switched to a new profile.
Indicates that Ref AA has been validated.
Indicates that Ref AA has been cleared of a previous fault.
Indicates that Ref AA has been faulted.
Indicates that Ref A has switched to a new profile.
Indicates that Ref A has been validated.
Indicates that Ref A has been cleared of a previous fault.
Indicates that Ref A has been faulted.
Indicates that Ref BB has switched to a new profile.
Indicates that Ref BB has been validated.
Indicates that Ref BB has been cleared of a previous fault.
Indicates that Ref BB has been faulted.
Indicates that Ref B has switched to a new profile.
Indicates that Ref B has been validated.
Indicates that Ref B has been cleared of a previous fault.
Indicates that Ref B has been faulted.
Unused.
Description
The current closed-loop phase offset is rate limited.
A phase build-out transition was made to the currently active reference.
The DPLL has achieved frequency lock.
The DPLL has achieved phase lock.
The DPLL is in the process of a reference switchover.
The DPLL is in holdover mode.
The DPLL is active (that is, operating in a closed-loop condition).
The DPLL is free running (that is, operating in an open-loop condition).
The upper or lower frequency tuning word clamp is in effect.
There is sufficient tuning word history available for holdover operation.
Priority value of the currently active reference.
Unused.
Index of the currently active reference.
000 = highest priority.
111 = lowest priority.
00 = Reference A.
01 = Reference AA.
10 = Reference B.
11 = Reference BB.
Rev. B | Page 93 of 104
AD9547