AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 64

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9547
Addr
0x06D4
0x06D5
0x06D6
0x06D7
0x06D8
0x06D9
0x06DA
0x06DB
0x06DC
0x06D
D
0x06DE
0x06DF
0x06E0
0x06E1
0x06E2
0x06E3
0x06E4
to
0x06FF
Profile Registers—Profile 4 through Profile 7
0x0700
to
0x07FF
Operational Controls
0x0A00
0x0A01
0x0A02
0x0A03
0x0A04
0x0A05
0x0A06
0x0A07
0x0A08
0x0A09
0x0A0A
0x0A0B
0x0A0C
0x0A0D
0x0A0E
0x0A0F
0x0A10
A, C
A, C
A, C
C
C
Opt
S
C
S
A, C
A, C
A, C
A, C
A, C
A, C
A, C
A, C
A, C
1
Name
S divider
Fractional
feedback
divider
Lock
detectors
Profile 4
through
Profile 7
General
power-down
Loop mode
Cal/sync
Reset
functions
IRQ clearing
Incremental
phase offset
Reference
profile selec-
tion state
machine
startup
Force
validation
timeout
Reference
monitor
override
Reference
monitor
bypass
D7
The functionality of the Profile 4 through Profile 7 address locations (Address 0x0700 to Address 0x07FF) is identical to
that of the Profile 0 through Profile 3 address locations (Address 0x0600 to Address 0x06FF)
Reset sans
regmap
Unused
Unused
Ref AA
new profile
Ref BB
new profile
Switching
Unused
Unused
D6
Unused
User
holdover
Clear LF
Closed
Ref AA
validated
Ref BB
validated
Unused
Unused
Unused
Unused
Unused
Unused
Unused
U[3:0]
D5
SYSCLK
power-
down
User
free run
SYSCLK
unlocked
Ref AA fault
cleared
Ref BB
fault cleared
Clear CCI
Free run
Unused
Rev. B | Page 64 of 104
Unused
Frequency lock threshold[23:0] (in ps)
Phase lock threshold[15:0] (in ps)
Frequency lock drain rate[7:0]
D4
Reference
power-
down
User selection mode[1:0]
Clear phase
accumulator
SYSCLK
locked
Holdover
History
updated
Ref AA fault
Ref BB
fault
Frequency lock fill rate[7:0]
Phase lock drain rate[7:0]
Phase lock fill rate[7:0]
Unused
Unused
Unused
Unused
S[15:0]
V[7:0]
D3
TDC
power-
down
Reset auto
sync
Distribu-
tion sync
Frequency
unlocked
Frequency
unclamped
Ref A
new profile
Ref B
new profile
Detect BB
Force
Timeout BB
Ref Mon
Override BB
Ref Mon
Bypass BB
Unused
Unused
U[9:4]
D2
DAC
power-
down
Reset
TW history
Watchdog
timer
Frequency
locked
Frequency
clamped
Ref A
validated
Ref B
validated
Reset
phase offset
Detect B
Force
Timeout B
Ref Mon
Override B
Ref Mon
Bypass B
to this bit)
(write a 0
Unused
S[19:16]
D1
Dist
power-
down
Sync
distribution
Reset
all IRQs
SYSCLK cal
complete
EEPROM
fault
Phase
unlocked
Phase slew
unlimited
Ref A
fault cleared
Ref B
fault cleared
Decrement
phase offset
Detect AA
Force
Timeout AA
Ref Mon
Override AA
Ref Mon
Bypass AA
User reference
selection[1:0]
V[9:8]
D0
Full
power-
down
Calibrate
SYSCLK
Reset
watchdog
SYSCLK cal
started
EEPROM
complete
Phase
locked
Phase slew
limited
Ref A
fault
Ref B
fault
Increment
phase offset
Detect A
Force
Timeout A
Ref Mon
Override A
Ref Mon
Bypass A
Def
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00