AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 38

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9547
The LF path permits the user to provide an LVPECL, LVDS,
CMOS, or sinusoidal low frequency clock for multiplication
by the integrated SYSCLK PLL. The LF path handles input
frequencies from 3.5 MHz up to 100 MHz. However, when
using a sinusoidal input signal, it is best to use a frequency in
excess of 20 MHz. Otherwise, the resulting low slew rate can
lead to substandard noise performance. Note that the LF path
includes an optional 2× frequency multiplier to double the rate
at the input to the SYSCLK PLL and potentially reduce the PLL
in-band noise. However, to avoid exceeding the maximum PFD
rate of 150 MHz, use of the 2× frequency multiplier is valid only
for input frequencies below 125 MHz.
The XTAL path enables the connection of a crystal resonator
(typically 10 MHz to 50 MHz) across the SYSCLKx input pins.
An internal amplifier provides the negative resistance required
to induce oscillation. The internal amplifier expects a 3.2 mm ×
2.5 mm AT cut, fundamental mode crystal with a maximum
motional resistance of 100 Ω. The following crystals, listed in
alphabetical order, may meet these criteria. Note that, although
these crystals meet the preceding criteria according to their data
sheets, Analog Devices, Inc., does not guarantee their opera-tion
with the AD9547, nor does Analog Devices endorse one crystal
manufacturer/supplier over another.
•
•
•
•
•
AVX/Kyocera CX3225SB
ECS ECX-32
Epson/Toyocom TSX-3225
NDK NX3225SA
Siward SX-3225
SYSCLKN
SYSCLKP
37
38
LF
HF
XTAL
÷M
2×
Figure 43. System Clock Block Diagram
Rev. B | Page 38 of 104
DETECT
CHARGE
LOCK
PUMP
AND
PFD
SYSCLK PLL MULTIPLIER
The SYSCLK PLL multiplier is an integer-N design and relies on
an integrated LC tank and VCO. It provides a means to convert
a low frequency clock input to the desired system clock frequency,
f
signals between 3.5 MHz and 500 MHz, but frequencies in excess
of 150 MHz require the M-divider to ensure compliance with
the maximum PFD rate (150 MHz). The PLL contains a feedback
divider (N) that is programmable for divide values between 6 and
255. The nominal VCO gain is 70 MHz/V.
Lock Detector
The SYSCLK PLL has a built-in lock detector. Register 0x0100,
Bit 2 determines whether the lock detector is active. When it
is active (default), the user controls the sensitivity of the lock
detector via the lock detect divider bits (Register 0x0100, Bits[1:0]).
Note that a value of zero must be written to the system clock
stability timer (Register 0x0106 to Register 0x0108) whenever
the lock detector is disabled (Register 0x0100, Bit 2 = 1).
The SYSCLK PLL phase detector operates at the PFD rate, which is
f
back signals are phase aligned (within a certain threshold range).
While the PLL is in the process of acquiring a lock condition,
the PFD samples typically consist of an arbitrary sequence of
in-phase and out-of-phase indications. As the PLL approaches
complete phase lock, the number of consecutive in-phase PFD
samples grows larger. Thus, one way of indicating a locked
condition is to count the number of consecutive in-phase PFD
samples and, if it exceeds a certain value, declare the PLL locked.
This is exactly the role of the lock detect divider bits. When the
lock detector is enabled (Register 0x0100, Bit 2 = 0), the lock detect
divider bits determine the number of consecutive in-phase
decisions that are required (128, 256, 512, or 1024) before the lock
detector declares a locked condition. The default setting is 128.
S
VCO
(900 MHz to 1 GHz). The SYSCLK PLL multiplier accepts input
SYSCLK_VREG
/N. Each PFD sample indicates whether the reference and feed-
34
FILTER
LOOP
÷N
SYSCLK_LF
CALIBRATION
35
VCO
SYSTEM
CLOCK