AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 74

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9547
CLOCK DISTRIBUTION OUTPUT CONFIGURATION (REGISTER 0x0400 TO REGISTER 0x0417)
Table 66. Distribution Settings
Address
0x0400
1
Table 67. Distribution Enable
Address
0x0401
Table 68. Distribution Synchronization
Address
0x0402
Table 69. Automatic Synchronization
Address
0x0403
When Bits [1:0] = 11, the clock distribution output enters a deep sleep mode.
Bit
[7:6]
5
4
[3:2]
1
0
Bit
[7:2]
1
0
Bit
[7:6]
[5:4]
[3:2]
1
0
Bit
[7:2]
[1:0]
Bit Name
Unused
External distribution resistor
Receiver mode
Unused
OUT1 power-down
OUT0 power-down
Bit Name
Unused
OUT1 enable
OUT0 enable
Bit Name
Unused
Sync source
Unused
OUT1 sync mask
OUT0 sync mask
Bit Name
Unused
Automatic sync mode
1
Description
Unused.
Output current control for the clock distribution outputs.
0 (default) = internal current setting resistor.
1 = external current setting resistor.
Clock distribution receiver mode.
0 (default) = normal operation.
1 = high frequency mode (super-Nyquist).
Write a 1 to these bits.
Power down clock distribution output OUT1.
0 (default) = normal operation.
1 = power down.
Power down clock distribution output OUT0.
0 (default) = normal operation.
1 = power-down.
Unused.
Enable the OUT1 driver.
0 (default) = disable.
1 = enable.
Enable the OUT0 driver.
0 (default) = disable.
1 = enable.
Unused.
Select the sync source for the clock distribution output channels.
00 (default) = direct.
01 = active reference.
10 = DPLL feedback edge.
11 = reserved.
Unused.
Mask the synchronous reset to the OUT1 divider.
0 (default) = unmasked.
1 = masked.
Mask the synchronous reset to the OUT0 divider.
0 (default) = unmasked.
1 = masked.
Unused.
Autosync mode.
00 (default) = disabled.
01 = sync on DPLL frequency lock.
10 = sync on DPLL phase lock.
11 = reserved.
Description
Description
Description
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